Arbitrary always precise frequency of 5 minutes to deal with, and no glitches, very good.

Packet : 103244834clk_div5.rar filelist
clk_div5\clk_div5.qpf
clk_div5\clk_div5.qsf
clk_div5\db\clk_div5.db_info
clk_div5\db\clk_div5.map.qmsg
clk_div5\db\clk_div5.fit.qmsg
clk_div5\db\clk_div5.cmp.cdb
clk_div5\db\clk_div5.rtlv.hdb
clk_div5\db\clk_div5.cbx.xml
clk_div5\db\clk_div5.hif
clk_div5\db\clk_div5.(0).cnf.cdb
clk_div5\db\clk_div5.(0).cnf.hdb
clk_div5\db\clk_div5.hier_info
clk_div5\db\clk_div5.rtlv_sg_swap.cdb
clk_div5\db\clk_div5.pre_map.hdb
clk_div5\db\clk_div5.rtlv_sg.cdb
clk_div5\db\clk_div5.pre_map.cdb
clk_div5\db\clk_div5.sgdiff.cdb
clk_div5\db\clk_div5.sgdiff.hdb
clk_div5\db\clk_div5.psp
clk_div5\db\clk_div5.dbp
clk_div5\db\clk_div5.map.cdb
clk_div5\db\clk_div5.map.hdb
clk_div5\db\clk_div5.asm.qmsg
clk_div5\db\clk_div5.syn_hier_info
clk_div5\db\clk_div5.signalprobe.cdb
clk_div5\db\clk_div5.tan.qmsg
clk_div5\db\clk_div5.sld_design_entry_dsc.sci
clk_div5\db\clk_div5.eco.cdb
clk_div5\db\clk_div5.cmp.tdb
clk_div5\db\clk_div5.cmp.hdb
clk_div5\db\clk_div5.eda.qmsg
clk_div5\db\clk_div5.cmp.rdb
clk_div5\db\clk_div5.cmp0.ddb
clk_div5\db\clk_div5.sld_design_entry.sci
clk_div5\db\clk_div5.sim.qmsg
clk_div5\db\clk_div5.sim.hdb
clk_div5\db\clk_div5.eds_overflow
clk_div5\db\clk_div5.sim.rdb
clk_div5\clk_div5.map.eqn
clk_div5\clk_div5.map.rpt
clk_div5\clk_div5.flow.rpt
clk_div5\clk_div5.map.summary
clk_div5\clk_div5.fit.eqn
clk_div5\clk_div5.pin
clk_div5\clk_div5.fit.rpt
clk_div5\clk_div5.fit.summary
clk_div5\clk_div5.sof
clk_div5\clk_div5.pof
clk_div5\clk_div5.asm.rpt
clk_div5\clk_div5.tan.summary
clk_div5\clk_div5.tan.rpt
clk_div5\simulation\modelsim\clk_div5_modelsim.xrf
clk_div5\simulation\modelsim\clk_div5.vho
clk_div5\simulation\modelsim\clk_div5_vhd.sdo
clk_div5\clk_div5.eda.rpt
clk_div5\clk_div5.done
clk_div5\clk_div5.vwf
clk_div5\clk_div5.sim.rpt
clk_div5\clk_div5.bsf
clk_div5\clk_div5.qws
clk_div5\clk_div5.vhd
clk_div5\simulation\modelsim
clk_div5\db
clk_div5\simulation
clk_div5

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