Introduction - If you have any usage issues, please Google them yourself
Matlab software programming DDS (direct digital frequency synthesis). Clock frequency set to a fixed value f_C, under the effect of CLK, according to 0000,, ..., 1111 of the sequence of addresses in the ROM reads the data, i.e., the amplitude of the encoding in Table 1, the frequency of the sinusoidal signal f_01 if every time a read address data (ie 0000,0001,0100, ..., the order of 1110), the output signal frequency is f_02, and f_02 f_01 than doubled, i.e. f_02 = 2f_01 rest on. This allows direct digital frequency synthesizer output frequency regulation.