Based on VHDL square wave triangle wave conversion program

project2\db\logic_util_heursitic.dat
........\..\prev_cmp_project2.qmsg
........\..\project2.db_info
........\..\project2.sld_design_entry.sci
........\incremental_db\compiled_partitions\project2.db_info
........\..............\README
........\key_en.vhd
........\key_en.vhd.bak
........\led.vhd
........\led.vhd.bak
........\project2.asm.rpt
........\project2.cdf
........\project2.done
........\project2.eda.rpt
........\project2.fit.rpt
........\project2.fit.smsg
........\project2.fit.summary
........\project2.flow.rpt
........\project2.jdi
........\project2.map.rpt
........\project2.map.summary
........\project2.pin
........\project2.pof
........\project2.qpf
........\project2.qsf
........\project2.qws
........\project2.sof
........\project2.sta.rpt
........\project2.sta.summary
........\project2.vhd
........\project2.vhd.bak
........\project2_assignment_defaults.qdf
........\simulation\modelsim\project2.sft
........\..........\........\project2.vo
........\..........\........\project2_fast.vo
........\..........\........\project2_modelsim.xrf
........\..........\........\project2_v.sdo
........\..........\........\project2_v_fast.sdo
........\..........\qsim\project2.do
........\..........\....\project2.msim.vcd
........\..........\....\project2.msim.vwf
........\..........\....\project2.sim.vwf
........\..........\....\project2.vo
........\..........\....\project2.vt
........\..........\....\project2_v.sdo
........\..........\....\project2_v.sdo_typ.csd
........\..........\....\transcript
........\..........\....\vsim.wlf
........\..........\....\work\project2\verilog.prw
........\..........\....\....\........\verilog.psm
........\..........\....\....\........\_primary.dat
........\..........\....\....\........\_primary.dbs
........\..........\....\....\........\_primary.vhd
........\..........\....\....\........_vlg_check_tst\verilog.prw
........\..........\....\....\......................\verilog.psm
........\..........\....\....\......................\_primary.dat
........\..........\....\....\......................\_primary.dbs
........\..........\....\....\......................\_primary.vhd
........\..........\....\....\.............sample_tst\verilog.prw
........\..........\....\....\.......................\verilog.psm
........\..........\....\....\.......................\_primary.dat
........\..........\....\....\.......................\_primary.dbs
........\..........\....\....\.......................\_primary.vhd
........\..........\....\....\.............vec_tst\verilog.prw
........\..........\....\....\....................\verilog.psm
........\..........\....\....\....................\_primary.dat
........\..........\....\....\....................\_primary.dbs
........\..........\....\....\....................\_primary.vhd
........\..........\....\....\_info
........\..........\....\....\_vmake
........\Waveform.vwf
Lorenz1\aes.bsf
.......\aes.v
.......\AES_ctrl.bsf
.......\AES_ctrl.vhd
.......\AES_ctrl.vhd.bak
.......\AES_dec.bsf
.......\AES_dec.vhd
.......\AES_dec.vhd.bak
.......\AES_IO.bsf
.......\AES_IO.vhd
.......\AES_IO.vhd.bak
.......\AES_key.bsf
.......\AES_key.vhd
.......\AES_key.vhd.bak
.......\AES_test.bdf
.......\AUDIO_DAC_FIFO.v
.......\audio_pll.bsf
.......\audio_pll.v
.......\Block1.bdf
.......\byte_mixcolum.v
.......\Chen_wave.bsf
.......\Chen_wave.vhd
.......\Chen_wave.vhd.bak
.......\db\add_sub_4jh.tdf
.......\..\add_sub_6jh.tdf
.......\..\add_sub_7jh.tdf
.......\..\add_sub_8jh.tdf
.......\..\add_sub_9jh.tdf
.......\..\add_sub_a8h.tdf

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