Written using Verilog HDL uart program, pro-test is feasible, very detailed notes!

18.uart\rx_fifo_module.qip
.......\rx_fifo_module.v
.......\rx_fifo_module_bb.v
.......\rx_fifo_module_inst.v
.......\tx_fifo_module.qip
.......\tx_fifo_module.v
.......\tx_fifo_module_bb.v
.......\tx_fifo_module_inst.v
.......\uart.cdf
.......\uart.done
.......\uart.fit.smsg
.......\uart.fit.summary
.......\uart.map.summary
.......\uart.pin
.......\uart.pof
.......\uart.qpf
.......\uart.qsf
.......\uart.sof
.......\tcl\18_osh.tcl
.......\source\detect_module.v
.......\......\detect_module.v.bak
.......\......\inter_control_module.v
.......\......\inter_control_module.v.bak
.......\......\rx_bps_module.v
.......\......\rx_control_module.v
.......\......\rx_control_module.v.bak
.......\......\rx_fifo_module.qip
.......\......\rx_interface.v
.......\......\rx_interface.v.bak
.......\......\rx_module.v
.......\......\rx_module.v.bak
.......\......\rx_top_control_module.v
.......\......\rx_top_control_module.v.bak
.......\......\rx_tx_interface_demo.v
.......\......\rx_tx_interface_demo.v.bak
.......\......\tx_bps_module.v
.......\......\tx_bps_module.v.bak
.......\......\tx_control_module.v
.......\......\tx_control_module.v.bak
.......\......\tx_fifo_module.qip
.......\......\tx_interface.v
.......\......\tx_interface.v.bak
.......\......\tx_module.v
.......\......\tx_module.v.bak
.......\......\tx_top_control_module.v
.......\......\greybox_tmp\cbx_args.txt
.......\incremental_db\README
.......\..............\compiled_partitions\uart.root_partition.cmp.kpt
.......\..............\...................\uart.root_partition.cmp.logdb
.......\..............\...................\uart.root_partition.map.kpt
.......\..............\...................\uart.db_info
.......\..............\...................\uart.root_partition.map.dpi
.......\..............\...................\uart.root_partition.map.cdb
.......\..............\...................\uart.root_partition.map.hdb
.......\..............\...................\uart.root_partition.map.hbdb.hb_info
.......\..............\...................\uart.root_partition.map.hbdb.cdb
.......\..............\...................\uart.root_partition.map.hbdb.hdb
.......\..............\...................\uart.root_partition.map.hbdb.sig
.......\..............\...................\uart.root_partition.cmp.rcfdb
.......\..............\...................\uart.root_partition.cmp.cdb
.......\..............\...................\uart.root_partition.cmp.hdb
.......\..............\...................\uart.root_partition.cmp.dfp
.......\db\altsyncram_q0k1.tdf
.......\..\a_dpfifo_ca31.tdf
.......\..\a_fefifo_18e.tdf
.......\..\cntr_3ob.tdf
.......\..\cntr_fo7.tdf
.......\..\dpram_4711.tdf
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_uart.qmsg
.......\..\scfifo_5431.tdf
.......\..\uart.tiscmp.fast_1200mv_0c.ddb
.......\..\uart.sta.rdb
.......\..\uart.tis_db_list.ddb
.......\..\uart.tmw_info
.......\..\uart.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.......\..\uart.sld_design_entry.sci
.......\..\uart.asm.rdb
.......\..\uart.cmp.rdb
.......\..\uart.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.......\..\uart.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
.......\..\uart.db_info
.......\..\uart.map.qmsg
.......\..\uart.cbx.xml
.......\..\uart.hif
.......\..\uart.hier_info
.......\..\uart.rtlv_sg.cdb
.......\..\uart.smart_action.txt
.......\..\uart.rtlv.hdb
.......\..\uart.rtlv_sg_swap.cdb
.......\..\uart.lpc.txt
.......\..\uart.lpc.html
.......\..\uart.lpc.rdb
.......\..\uart.pre_map.hdb
.......\..\uart.pre_map.cdb
.......\..\uart.map_bb.logdb
.......\..\uart.sgdiff.cdb
.......\..\uart.sgdiff.hdb
.......\..\uart.sld_design_entry_dsc.sci
.......\..\uart.root_partition.map.reg_db.cdb

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