Verilog HDL serial program written examples, very good reference code in detail. In view of the Xilinx FPGA development board, in Xilinx ISE compiler debugging success, a serial port development of classic routines.

UART\impact.xsl
....\impact_impact.xwbt
....\.seconfig\UART.projectmgr
....\.........\uart.xreport
....\output.txt
....\pa.fromHdl.tcl
....\pa.fromNetlist.tcl
....\planAhead.ngc2edif.log
....\........._run_1\planAhead.jou
....\...............\planAhead.log
....\...............\planAhead_run.log
....\..............2\UART.data\constrs_1\fileset.xml
....\...............\.........\sources_1\fileset.xml
....\...............\.........\wt\webtalk_pa.xml
....\...............\UART.ppr
....\uart.bgn
....\uart.bit
....\uart.bld
....\uart.cmd_log
....\uart.drc
....\UART.gise
....\uart.lso
....\uart.ncd
....\uart.ngc
....\uart.ngd
....\uart.ngr
....\uart.pad
....\uart.par
....\uart.pcf
....\uart.prj
....\uart.ptwx
....\uart.stx
....\uart.syr
....\uart.twr
....\uart.twx
....\UART.ucf
....\uart.unroutes
....\uart.ut
....\uart.v
....\UART.xise
....\uart.xpi
....\uart.xst
....\uart_bitgen.xwbt
....\uart_envsettings.html
....\uart_guide.ncd
....\uart_map.map
....\uart_map.mrp
....\uart_map.ncd
....\uart_map.ngm
....\uart_map.xrpt
....\uart_ngdbuild.xrpt
....\uart_pad.csv
....\uart_pad.txt
....\uart_par.xrpt
....\uart_summary.html
....\uart_summary.xml
....\uart_usage.xml
....\uart_xst.xrpt
....\unknown_0_5.bsd
....\usage_statistics_webtalk.html
....\Verilog2.v
....\Verilog3.v
....\Verilog4.v
....\webtalk.log
....\webtalk_impact.xml
....\webtalk_pn.xml
....\xlnx_auto_0_xdb\cst.xbcd
....\.st\work\hdllib.ref
....\...\....\vlg20\speed__select.bin
....\...\....\....E\my__uart__rx.bin
....\...\....\...38\my__uart__tx.bin
....\...\....\...48\uart.bin
....\_ngo\netlist.lst
....\.xmsgs\bitgen.xmsgs
....\......\map.xmsgs
....\......\ngdbuild.xmsgs
....\......\par.xmsgs
....\......\pn_parser.xmsgs
....\......\trce.xmsgs
....\......\xst.xmsgs
....\xst\dump.xst\uart.prj\ngx\notopt
....\...\........\........\...\opt
....\...\........\........\ngx
....\planAhead_run_2\UART.data\constrs_1
....\...............\.........\sources_1
....\...............\.........\wt
....\xst\dump.xst\uart.prj
....\...\work\vlg20
....\...\....\vlg2E
....\...\....\vlg38
....\...\....\vlg48
....\planAhead_run_2\UART.data
....\xst\dump.xst
....\...\projnav.tmp
....\...\work
....\iseconfig
....\planAhead_run_1
....\planAhead_run_2
....\xlnx_auto_0_xdb
....\xst

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