Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full adder.

exp5\db\exp5.cbx.xml
....\..\exp5.cmp.cdb
....\..\exp5.cmp.hdb
....\..\exp5.cmp.logdb
....\..\exp5.cmp.rdb
....\..\exp5.db_info
....\..\exp5.eco.cdb
....\..\exp5.fit.qmsg
....\..\exp5.hier_info
....\..\exp5.hif
....\..\exp5.lpc.html
....\..\exp5.lpc.rdb
....\..\exp5.lpc.txt
....\..\exp5.map.cdb
....\..\exp5.map.hdb
....\..\exp5.map.logdb
....\..\exp5.map.qmsg
....\..\exp5.pre_map.cdb
....\..\exp5.pre_map.hdb
....\..\exp5.rtlv.hdb
....\..\exp5.rtlv_sg.cdb
....\..\exp5.rtlv_sg_swap.cdb
....\..\exp5.sgdiff.cdb
....\..\exp5.sgdiff.hdb
....\..\exp5.sim.cvwf
....\..\exp5.sld_design_entry.sci
....\..\exp5.sld_design_entry_dsc.sci
....\..\exp5.syn_hier_info
....\..\exp5.tis_db_list.ddb
....\..\exp5.tmw_info
....\..\prev_cmp_exp5.asm.qmsg
....\..\prev_cmp_exp5.fit.qmsg
....\..\prev_cmp_exp5.map.qmsg
....\..\prev_cmp_exp5.qmsg
....\..\prev_cmp_exp5.sim.qmsg
....\..\prev_cmp_exp5.tan.qmsg
....\..\wed.wsf
....\exp5.asm.rpt
....\exp5.cdf
....\exp5.done
....\exp5.dpf
....\exp5.fit.rpt
....\exp5.fit.summary
....\exp5.flow.rpt
....\exp5.map.rpt
....\exp5.map.summary
....\exp5.pin
....\exp5.pof
....\exp5.qpf
....\exp5.qsf
....\exp5.qws
....\exp5.sim.rpt
....\exp5.sof
....\exp5.tan.rpt
....\exp5.tan.summary
....\exp5.vhd.bak
....\exp5.vwf
....\exp5_assignment_defaults.qdf
....\FULL_4ADDER.vhd
....\FULL_4ADDER.vhd.bak
....\FULL_4ADDER.vwf
....\FULL_ADDER.vhd
....\FULL_ADDER.vhd.bak
....\FULL_ADDER.vwf
....\HALF_ADDER.vhd
....\HALF_ADDER.vhd.bak
....\incremental_db\compiled_partitions\exp5.root_partition.map.kpt
....\..............\README
....\prev_cmp_exp5.qmsg
....\serv_req_info.txt
....\incremental_db\compiled_partitions
....\db
....\incremental_db
exp5

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