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Count-clock-synthesis-experiments

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-09-16
  • Size : 172kb
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Introduction - If you have any usage issues, please Google them yourself
Exercise comprehensive design capabilities, including the design of a time/minutes/seconds of the clock, and you can set, clear, 12/24 hour work mode.
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Count clock synthesis experiments\exp 6\adder_10.vhd
.................................\.....\adder_10.vhd.bak
.................................\.....\adder_10.vwf
.................................\.....\adder_6.vhd
.................................\.....\adder_6.vhd.bak
.................................\.....\adder_6.vwf
.................................\.....\adder_60.vhd
.................................\.....\adder_60.vhd.bak
.................................\.....\adder_60.vwf
.................................\.....\adder_60_2.vhd
.................................\.....\adder_60_2.vhd.bak
.................................\.....\adde_60_2.vwf
.................................\.....\db\add_sub_anh.tdf
.................................\.....\..\add_sub_bnh.tdf
.................................\.....\..\add_sub_dnh.tdf
.................................\.....\..\exp6.asm.qmsg
.................................\.....\..\exp6.cbx.xml
.................................\.....\..\exp6.cmp.cdb
.................................\.....\..\exp6.cmp.hdb
.................................\.....\..\exp6.cmp.logdb
.................................\.....\..\exp6.cmp.rdb
.................................\.....\..\exp6.cmp.tdb
.................................\.....\..\exp6.cmp0.ddb
.................................\.....\..\exp6.dbp
.................................\.....\..\exp6.db_info
.................................\.....\..\exp6.eco.cdb
.................................\.....\..\exp6.eds_overflow
.................................\.....\..\exp6.fit.qmsg
.................................\.....\..\exp6.fnsim.cdb
.................................\.....\..\exp6.fnsim.hdb
.................................\.....\..\exp6.fnsim.qmsg
.................................\.....\..\exp6.hier_info
.................................\.....\..\exp6.hif
.................................\.....\..\exp6.map.cdb
.................................\.....\..\exp6.map.hdb
.................................\.....\..\exp6.map.logdb
.................................\.....\..\exp6.map.qmsg
.................................\.....\..\exp6.pre_map.cdb
.................................\.....\..\exp6.pre_map.hdb
.................................\.....\..\exp6.psp
.................................\.....\..\exp6.pss
.................................\.....\..\exp6.rtlv.hdb
.................................\.....\..\exp6.rtlv_sg.cdb
.................................\.....\..\exp6.rtlv_sg_swap.cdb
.................................\.....\..\exp6.sgdiff.cdb
.................................\.....\..\exp6.sgdiff.hdb
.................................\.....\..\exp6.sim.cvwf
.................................\.....\..\exp6.sim.hdb
.................................\.....\..\exp6.sim.qmsg
.................................\.....\..\exp6.sim.rdb
.................................\.....\..\exp6.sld_design_entry.sci
.................................\.....\..\exp6.sld_design_entry_dsc.sci
.................................\.....\..\exp6.syn_hier_info
.................................\.....\..\exp6.tan.qmsg
.................................\.....\..\prev_cmp_exp6.asm.qmsg
.................................\.....\..\prev_cmp_exp6.fit.qmsg
.................................\.....\..\prev_cmp_exp6.map.qmsg
.................................\.....\..\prev_cmp_exp6.sim.qmsg
.................................\.....\..\prev_cmp_exp6.tan.qmsg
.................................\.....\..\wed.wsf
.................................\.....\exp6.asm.rpt
.................................\.....\exp6.cdf
.................................\.....\exp6.done
.................................\.....\exp6.dpf
.................................\.....\exp6.fit.rpt
.................................\.....\exp6.fit.summary
.................................\.....\exp6.flow.rpt
.................................\.....\exp6.map.rpt
.................................\.....\exp6.map.summary
.................................\.....\exp6.pin
.................................\.....\exp6.pof
.................................\.....\exp6.qpf
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