Using Verilog language to complete the FPGA DM9000A driver based on 10M/100M communication, complete with the PC

DM9000A&PC\db\altsyncram_2p01.tdf
..........\..\MainBoard.ace_cmp.bpm
..........\..\MainBoard.ace_cmp.cdb
..........\..\MainBoard.ace_cmp.ecobp
..........\..\MainBoard.ace_cmp.hdb
..........\..\MainBoard.asm.qmsg
..........\..\MainBoard.asm_labs.ddb
..........\..\MainBoard.cbx.xml
..........\..\MainBoard.cmp.bpm
..........\..\MainBoard.cmp.cdb
..........\..\MainBoard.cmp.ecobp
..........\..\MainBoard.cmp.hdb
..........\..\MainBoard.cmp.kpt
..........\..\MainBoard.cmp.logdb
..........\..\MainBoard.cmp.rdb
..........\..\MainBoard.cmp_merge.kpt
..........\..\MainBoard.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
..........\..\MainBoard.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
..........\..\MainBoard.db_info
..........\..\MainBoard.eco.cdb
..........\..\MainBoard.fit.qmsg
..........\..\MainBoard.hier_info
..........\..\MainBoard.hif
..........\..\MainBoard.lpc.html
..........\..\MainBoard.lpc.rdb
..........\..\MainBoard.lpc.txt
..........\..\MainBoard.MainBoard0.rtl.mif
..........\..\MainBoard.map.bpm
..........\..\MainBoard.map.cdb
..........\..\MainBoard.map.ecobp
..........\..\MainBoard.map.hdb
..........\..\MainBoard.map.kpt
..........\..\MainBoard.map.logdb
..........\..\MainBoard.map.qmsg
..........\..\MainBoard.map_bb.cdb
..........\..\MainBoard.map_bb.hdb
..........\..\MainBoard.map_bb.logdb
..........\..\MainBoard.pre_map.cdb
..........\..\MainBoard.pre_map.hdb
..........\..\MainBoard.rtlv.hdb
..........\..\MainBoard.rtlv_sg.cdb
..........\..\MainBoard.rtlv_sg_swap.cdb
..........\..\MainBoard.sgdiff.cdb
..........\..\MainBoard.sgdiff.hdb
..........\..\MainBoard.sld_design_entry.sci
..........\..\MainBoard.sld_design_entry_dsc.sci
..........\..\MainBoard.smp_dump.txt
..........\..\MainBoard.sta.qmsg
..........\..\MainBoard.sta.rdb
..........\..\MainBoard.sta_cmp.8_slow_1200mv_85c.tdb
..........\..\MainBoard.syn_hier_info
..........\..\MainBoard.tiscmp.fast_1200mv_0c.ddb
..........\..\MainBoard.tiscmp.slow_1200mv_0c.ddb
..........\..\MainBoard.tiscmp.slow_1200mv_85c.ddb
..........\..\MainBoard.tis_db_list.ddb
..........\..\MainBoard.tmw_info
..........\..\MainBoard_global_asgn_op.abo
..........\..\prev_cmp_MainBoard.asm.qmsg
..........\..\prev_cmp_MainBoard.fit.qmsg
..........\..\prev_cmp_MainBoard.map.qmsg
..........\..\prev_cmp_MainBoard.qmsg
..........\..\prev_cmp_MainBoard.sta.qmsg
..........\incremental_db\compiled_partitions\MainBoard.root_partition.cmp.atm
..........\..............\...................\MainBoard.root_partition.cmp.dfp
..........\..............\...................\MainBoard.root_partition.cmp.hdbx
..........\..............\...................\MainBoard.root_partition.cmp.kpt
..........\..............\...................\MainBoard.root_partition.cmp.logdb
..........\..............\...................\MainBoard.root_partition.cmp.rcf
..........\..............\...................\MainBoard.root_partition.map.atm
..........\..............\...................\MainBoard.root_partition.map.dpi
..........\..............\...................\MainBoard.root_partition.map.hdbx
..........\..............\...................\MainBoard.root_partition.map.kpt
..........\..............\README
..........\MainBoard.asm.rpt
..........\MainBoard.cdf
..........\MainBoard.done
..........\MainBoard.dpf
..........\MainBoard.fit.rpt
..........\MainBoard.fit.smsg
..........\MainBoard.fit.summary
..........\MainBoard.flow.rpt
..........\MainBoard.map.rpt
..........\MainBoard.map.summary
..........\MainBoard.pin
..........\MainBoard.pof
..........\MainBoard.qpf
..........\MainBoard.qsf
..........\MainBoard.qws
..........\MainBoard.sof
..........\MainBoard.sta.rpt
..........\MainBoard.sta.summary
..........\MainBoard.v
..........\MainBoard.v.bak
..........\ParamsofMainBoard.H
..........\ParamsofMainBoard.H.bak
..........\incremental_db\compiled_partitions
..........\db
..........\incremental_db
DM9000A&PC

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