Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.

功能调试CPU
...........\db
...........\..\exp_cpu.db_info
...........\..\exp_cpu.eco.cdb
...........\..\exp_cpu.sld_design_entry.sci
...........\..\mult_nn01.tdf
...........\..\prev_cmp_exp_cpu.asm.qmsg
...........\..\prev_cmp_exp_cpu.eda.qmsg
...........\..\prev_cmp_exp_cpu.fit.qmsg
...........\..\prev_cmp_exp_cpu.map.qmsg
...........\..\prev_cmp_exp_cpu.qmsg
...........\..\prev_cmp_exp_cpu.tan.qmsg
...........\decoder_2_to_4.vhd
...........\decoder_unit.vhd
...........\decoder_unit.vhd.bak
...........\decorder2.vhd
...........\exe_unit.vhd
...........\exe_unit.vhd.bak
...........\exe_unit1.vhd
...........\exe_unit1.vhd.bak
...........\exp_cpu.asm.rpt
...........\exp_cpu.cdf
...........\exp_cpu.done
...........\exp_cpu.dpf
...........\exp_cpu.eda.rpt
...........\exp_cpu.fit.rpt
...........\exp_cpu.fit.smsg
...........\exp_cpu.fit.summary
...........\exp_cpu.flow.rpt
...........\exp_cpu.map.rpt
...........\exp_cpu.map.summary
...........\exp_cpu.pin
...........\exp_cpu.pof
...........\exp_cpu.qpf
...........\exp_cpu.qsf
...........\exp_cpu.qws
...........\exp_cpu.sof
...........\exp_cpu.tan.rpt
...........\exp_cpu.tan.summary
...........\exp_cpu.vhd
...........\exp_cpu.vhd.bak
...........\exp_cpu_assignment_defaults.qdf
...........\exp_cpu_components.vhd
...........\exp_cpu_components.vhd.bak
...........\forwarding_unit.vhd
...........\forwarding_unit.vhd.bak
...........\hazard_unit.vhd
...........\hazard_unit.vhd.bak
...........\hazarddetect_unit.vhd
...........\hazarddetect_unit.vhd.bak
...........\instru_fetch.vhd
...........\instru_fetch.vhd.bak
...........\memory_unit.vhd
...........\memory_unit.vhd.bak
...........\mux_4_to_1.vhd
...........\mux_exe_unit.vhd
...........\mux_exe_unit.vhd.bak
...........\reg.vhd
...........\reg1.vhd
...........\reg1.vhd.bak
...........\regfile.vhd
...........\regfile.vhd.bak
...........\simulation
...........\..........\activehdl
...........\..........\.........\exp_cpu.vo
...........\..........\.........\exp_cpu_v.sdo
...........\timing
...........\......\primetime
...........\......\.........\exp_cpu.vho
...........\......\.........\exp_cpu_pt_vhd.tcl
...........\......\.........\exp_cpu_vhd.sdo
...........\undo_redo.txt
...........\write_reg_unit.vhd
...........\write_reg_unit.vhd.bak
...........\五级流水线CPU VHDL代码
...........\......................\功能调试CPU搞定版
...........\......................\.................\CPU
...........\......................\.................\...\Block1.bdf
...........\......................\.................\...\Block2.bdf
...........\......................\.................\...\CPU.bdf
...........\......................\.................\...\db
...........\......................\.................\...\..\exp_cpu.db_info
...........\......................\.................\...\..\mult_nn01.tdf
...........\......................\.................\...\..\prev_cmp_exp_cpu.asm.qmsg
...........\......................\.................\...\..\prev_cmp_exp_cpu.eda.qmsg
...........\......................\.................\...\..\prev_cmp_exp_cpu.fit.qmsg
...........\......................\.................\...\..\prev_cmp_exp_cpu.map.qmsg
...........\......................\.................\...\..\prev_cmp_exp_cpu.qmsg
...........\......................\.................\...\..\prev_cmp_exp_cpu.tan.qmsg
...........\......................\.................\...\decoder_2_to_4.vhd
...........\......................\.................\...\decoder_unit.bsf
...........\......................\.................\...\decoder_unit.vhd
...........\......................\.................\...\decoder_unit.vhd.bak
...........\......................\.................\...\decorder2.vhd
...........\......................\.................\...\exe_unit.bsf
...........\......................\.................\...\exe_unit.vhd
...........\......................\.................\...\exe_unit.vhd.bak
...........\......................\.................\...\exe_unit1.vhd
...........\......................\.................\...\exe_unit1.vhd.bak
...........\...............

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