FPGA-based frequency meter, using verilog language, the standard clock counted to obtain the frequency of the signal.

freq\cmp_state.ini
....\count32.v
....\count8.v
....\db\fre.asm.qmsg
....\..\fre.cbx.xml
....\..\fre.cmp.cdb
....\..\fre.cmp.hdb
....\..\fre.cmp.logdb
....\..\fre.cmp.rdb
....\..\fre.cmp.tdb
....\..\fre.cmp0.ddb
....\..\fre.db_info
....\..\fre.eco.cdb
....\..\fre.fit.qmsg
....\..\fre.hier_info
....\..\fre.hif
....\..\fre.lpc.html
....\..\fre.lpc.rdb
....\..\fre.lpc.txt
....\..\fre.map.cdb
....\..\fre.map.hdb
....\..\fre.map.logdb
....\..\fre.map.qmsg
....\..\fre.pre_map.cdb
....\..\fre.pre_map.hdb
....\..\fre.rtlv.hdb
....\..\fre.rtlv_sg.cdb
....\..\fre.rtlv_sg_swap.cdb
....\..\fre.sgdiff.cdb
....\..\fre.sgdiff.hdb
....\..\fre.sld_design_entry.sci
....\..\fre.sld_design_entry_dsc.sci
....\..\fre.syn_hier_info
....\..\fre.tan.qmsg
....\..\fre.tis_db_list.ddb
....\..\fre.tmw_info
....\..\fre_cmp.qrpt
....\decoder.v
....\fre.asm.rpt
....\fre.cdf
....\fre.done
....\fre.fit.eqn
....\fre.fit.rpt
....\fre.fit.summary
....\fre.flow.rpt
....\fre.map.eqn
....\fre.map.rpt
....\fre.map.summary
....\fre.pin
....\fre.pof
....\fre.qsf
....\fre.sof
....\fre.tan.rpt
....\fre.tan.summary
....\fre.v
....\fre_assignment_defaults.qdf
....\fre_ctrl.v
....\incremental_db\compiled_partitions\fre.root_partition.map.kpt
....\..............\README
....\latch32.v
....\segscan.v
....\test1.qpf
....\test1.qws
....\incremental_db\compiled_partitions
....\db
....\incremental_db
freq

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