NIOS achieve uart transmission, write verilog language-based, black gold development board

NIOS_HELLO - uart
.................\.qsys_edit
.................\..........\filters.xml
.................\..........\kernel.xml
.................\..........\layout.xml
.................\..........\preferences.xml
.................\.sopc_builder
.................\.............\filters.xml
.................\.............\install.ptf
.................\.............\install2.ptf
.................\.............\preferences.xml
.................\assignment_defaults.qdf
.................\cpu.v
.................\cpu_bht_ram.mif
.................\cpu_ic_tag_ram.mif
.................\cpu_jtag_debug_module_sysclk.v
.................\cpu_jtag_debug_module_tck.v
.................\cpu_jtag_debug_module_wrapper.v
.................\cpu_mult_cell.v
.................\cpu_ociram_default_contents.mif
.................\cpu_oci_test_bench.v
.................\cpu_rf_ram_a.mif
.................\cpu_rf_ram_b.mif
.................\cpu_test_bench.v
.................\db
.................\..\.cmp.kpt
.................\..\add_sub_qvi.tdf
.................\..\altera_mult_add_q1u2.v
.................\..\altera_mult_add_s1u2.v
.................\..\altsyncram_0a02.tdf
.................\..\altsyncram_b7f1.tdf
.................\..\altsyncram_bgg1.tdf
.................\..\altsyncram_bpf1.tdf
.................\..\altsyncram_buf1.tdf
.................\..\altsyncram_c7f1.tdf
.................\..\altsyncram_cjd1.tdf
.................\..\altsyncram_cuf1.tdf
.................\..\altsyncram_f572.tdf
.................\..\altsyncram_k5g1.tdf
.................\..\altsyncram_ksg1.tdf
.................\..\altsyncram_l881.tdf
.................\..\altsyncram_m841.tdf
.................\..\altsyncram_r1m1.tdf
.................\..\altsyncram_sc31.tdf
.................\..\a_dpfifo_q131.tdf
.................\..\a_fefifo_7cf.tdf
.................\..\cntr_1ob.tdf
.................\..\cntr_do7.tdf
.................\..\ded_mult_ks81.tdf
.................\..\dffpipe_93c.tdf
.................\..\dpram_nl21.tdf
.................\..\HELLO.asm.qmsg
.................\..\HELLO.asm.rdb
.................\..\HELLO.asm_labs.ddb
.................\..\HELLO.autoh_e40e1.map.reg_db.cdb
.................\..\HELLO.cbx.xml
.................\..\HELLO.cmp.bpm
.................\..\HELLO.cmp.cdb
.................\..\HELLO.cmp.hdb
.................\..\HELLO.cmp.idb
.................\..\HELLO.cmp.logdb
.................\..\HELLO.cmp.rdb
.................\..\HELLO.cmp_merge.kpt
.................\..\HELLO.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.................\..\HELLO.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
.................\..\HELLO.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.................\..\HELLO.db_info
.................\..\HELLO.fit.qmsg
.................\..\HELLO.hier_info
.................\..\HELLO.hif
.................\..\HELLO.ipinfo
.................\..\HELLO.lpc.html
.................\..\HELLO.lpc.rdb
.................\..\HELLO.lpc.txt
.................\..\HELLO.map.ammdb
.................\..\HELLO.map.bpm
.................\..\HELLO.map.cdb
.................\..\HELLO.map.hdb
.................\..\HELLO.map.kpt
.................\..\HELLO.map.logdb
.................\..\HELLO.map.qmsg
.................\..\HELLO.map.rdb
.................\..\HELLO.map_bb.cdb
.................\..\HELLO.map_bb.hdb
.................\..\HELLO.map_bb.logdb
.................\..\HELLO.mif_update.qmsg
.................\..\HELLO.npp.qmsg
.................\..\HELLO.pplq.rdb
.................\..\HELLO.pre_map.hdb
.................\..\HELLO.pti_db_list.ddb
.................\..\HELLO.root_partition.map.reg_db.cdb
.................\..\HELLO.routing.rdb
.................\..\HELLO.rtlv.hdb
.................\..\HELLO.rtlv_sg.cdb
.................\..\HELLO.rtlv_sg_swap.cdb
.................\..\HELLO.sgdiff.cdb
.................\..\HELLO.sgdiff.hdb
.................\..\HELLO.sld_design_entry.sci
.................\..\HELLO.sld_design_entry_dsc.sci
.................\..\HELLO.smart_action.txt

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