Based on the digital receiver, DSPK demodulation technology of FPGA implementation, is a complete project, very conducive to learning.

Dpsk\dpsk\CodeTransform.vhd
....\....\CodeTransform.vhi
....\....\CodeTransform_summary.html
....\....\Costas.bld
....\....\Costas.ncd
....\....\Costas.ngd
....\....\Costas.pad
....\....\Costas.par
....\....\Costas.pcf
....\....\Costas.ptwx
....\....\Costas.twr
....\....\Costas.twx
....\....\Costas.ucf
....\....\Costas.udo
....\....\Costas.unroutes
....\....\Costas.vhd
....\....\Costas.vhi
....\....\Costas.xpi
....\....\Costas_guide.ncd
....\....\Costas_map.map
....\....\Costas_map.mrp
....\....\Costas_map.ncd
....\....\Costas_map.xrpt
....\....\Costas_ngdbuild.xrpt
....\....\Costas_pad.csv
....\....\Costas_pad.txt
....\....\Costas_par.xrpt
....\....\Costas_summary.html
....\....\Costas_summary.xml
....\....\Costas_usage.xml
....\....\Costas_wave.fdo
....\....\DPSK.bld
....\....\DPSK.cmd_log
....\....\dpsk.gise
....\....\dpsk.ise
....\....\DPSK.lso
....\....\DPSK.ncd
....\....\DPSK.ngc
....\....\DPSK.ngd
....\....\DPSK.ngr
....\....\dpsk.ntrc_log
....\....\DPSK.pad
....\....\DPSK.par
....\....\DPSK.pcf
....\....\DPSK.prj
....\....\DPSK.ptwx
....\....\DPSK.stx
....\....\DPSK.syr
....\....\DPSK.twr
....\....\DPSK.twx
....\....\DPSK.ucf
....\....\DPSK.unroutes
....\....\dpsk.vhd
....\....\dpsk.xise
....\....\DPSK.xpi
....\....\DPSK.xst
....\....\DPSK_guide.ncd
....\....\DPSK_map.map
....\....\DPSK_map.mrp
....\....\DPSK_map.ncd
....\....\DPSK_map.xrpt
....\....\DPSK_ngdbuild.xrpt
....\....\DPSK_pad.csv
....\....\DPSK_pad.txt
....\....\DPSK_par.xrpt
....\....\DPSK_summary.html
....\....\DPSK_summary.xml
....\....\DPSK_usage.xml
....\....\dpsk_xdb\cst.xbcd
....\....\........\tmp\ise\version
....\....\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
....\....\........\...\...\............\..................\.........\HDProject_StrTbl
....\....\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
....\....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
....\....\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
....\....\........\...\...\............\................\................\dpm_project_main_StrTbl
....\....\........\...\...\............\................Gui\CSourceProcessView
....\....\........\...\...\............\...................\CSourceProcessView_StrTbl
....\....\........\...\...\............\...................\CViewSelector
....\....\........\...\...\............\...................\CViewSelector_StrTbl
....\....\........\...\...\............\...................\File-SynthesisOnly
....\....\........\...\...\............\...................\File-SynthesisOnly_StrTbl
....\....\........\...\...\............\...................\Library-SynthesisOnly
....\....\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
....\....\........\...\...\............\...................\Process-BehavioralSim-
....\....\........\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE
....\....\........\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl
....\....\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
....\....\........\...\...\............\...................\Process-PostRouteSim-
....\....\........\...\...\............\...................\Process-PostRouteSim-DESUT_VHDL_ARCHITECTURE
....\....\........\...\...\............\...................\Process-PostRouteSim-DESUT_VHDL_ARCHITECTURE_StrTbl
....\....\........\...\...\............\...................\Process-PostRouteSim-_StrTbl
....\....\........\...\...\............\...................\Process-SynthesisOnly-
....\....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF
....\....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl
....\....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
....\....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
....\....\........\...\...\............\.........

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