this is a clock generator program by using concurrent language verilog hdl with xilinx ise.

clk_gen\.lso
.......\clk_gen.cmd_log
.......\clk_gen.fdo
.......\clk_gen.gise
.......\clk_gen.lso
.......\clk_gen.prj
.......\clk_gen.syr
.......\clk_gen.udo
.......\clk_gen.v
.......\clk_gen.xise
.......\clk_gen.xst
.......\clk_gen_envsettings.html
.......\clk_gen_summary.html
.......\clk_gen_wave.fdo
.......\clk_gen_xst.xrpt
.......\iseconfig\clk_gen.projectmgr
.......\.........\clk_gen.xreport
.......\transcript
.......\vsim.wlf
.......\webtalk_pn.xml
.......\.ork\clk_gen\verilog.psm
.......\....\.......\_primary.dat
.......\....\.......\_primary.dbs
.......\....\.......\_primary.vhd
.......\....\glbl\verilog.psm
.......\....\....\_primary.dat
.......\....\....\_primary.dbs
.......\....\....\_primary.vhd
.......\....\_info
.......\xst\work\hdllib.ref
.......\...\....\vlg6B\clk__gen.bin
.......\_xmsgs\pn_parser.xmsgs
.......\......\xst.xmsgs
.......\xst\dump.xst\clk_gen.prj\ngx\notopt
.......\...\........\...........\...\opt
.......\...\........\...........\ngx
.......\...\........\clk_gen.prj
.......\...\work\vlg6B
.......\work\clk_gen
.......\....\glbl
.......\....\_temp
.......\xst\dump.xst
.......\...\projnav.tmp
.......\...\work
.......\iseconfig
.......\work
.......\xst
.......\_xmsgs
clk_gen

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