FPGA clock display program, you can follow the normal time, frequency adjustable, digital display 00-00-00, middle- can be changed. As long as the use of a nested loop structure to achieve

Clock\clock.asm.rpt
.....\clock.cdf
.....\clock.done
.....\clock.eda.rpt
.....\clock.fit.rpt
.....\clock.fit.smsg
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.jdi
.....\clock.map.rpt
.....\clock.map.summary
.....\clock.pin
.....\clock.qpf
.....\clock.qsf
.....\clock.sof
.....\clock.sta.rpt
.....\clock.sta.summary
.....\clock.v
.....\clock.v.bak
.....\simulation\modelsim\clock.sft
.....\..........\........\clock.vho
.....\..........\........\clock_8_1200mv_0c_slow.vho
.....\..........\........\clock_8_1200mv_0c_vhd_slow.sdo
.....\..........\........\clock_8_1200mv_85c_slow.vho
.....\..........\........\clock_8_1200mv_85c_vhd_slow.sdo
.....\..........\........\clock_min_1200mv_0c_fast.vho
.....\..........\........\clock_min_1200mv_0c_vhd_fast.sdo
.....\..........\........\clock_modelsim.xrf
.....\..........\........\clock_vhd.sdo
.....\incremental_db\README
.....\..............\compiled_partitions\clock.db_info
.....\..............\...................\clock.root_partition.cmp.cdb
.....\..............\...................\clock.root_partition.cmp.dfp
.....\..............\...................\clock.root_partition.cmp.hdb
.....\..............\...................\clock.root_partition.cmp.kpt
.....\..............\...................\clock.root_partition.cmp.logdb
.....\..............\...................\clock.root_partition.cmp.rcfdb
.....\..............\...................\clock.root_partition.map.cdb
.....\..............\...................\clock.root_partition.map.dpi
.....\..............\...................\clock.root_partition.map.hbdb.cdb
.....\..............\...................\clock.root_partition.map.hbdb.hb_info
.....\..............\...................\clock.root_partition.map.hbdb.hdb
.....\..............\...................\clock.root_partition.map.hbdb.sig
.....\..............\...................\clock.root_partition.map.hdb
.....\..............\...................\clock.root_partition.map.kpt
.....\db\clock.amm.cdb
.....\..\clock.asm.qmsg
.....\..\clock.asm.rdb
.....\..\clock.asm_labs.ddb
.....\..\clock.cbx.xml
.....\..\clock.cmp.bpm
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.kpt
.....\..\clock.cmp.logdb
.....\..\clock.cmp.rdb
.....\..\clock.cmp_merge.kpt
.....\..\clock.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.....\..\clock.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.....\..\clock.db_info
.....\..\clock.eda.qmsg
.....\..\clock.fit.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.idb.cdb
.....\..\clock.lpc.html
.....\..\clock.lpc.rdb
.....\..\clock.lpc.txt
.....\..\clock.map.bpm
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.kpt
.....\..\clock.map.logdb
.....\..\clock.map.qmsg
.....\..\clock.map_bb.cdb
.....\..\clock.map_bb.hdb
.....\..\clock.map_bb.logdb
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.root_partition.map.reg_db.cdb
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.smart_action.txt
.....\..\clock.sta.qmsg
.....\..\clock.sta.rdb
.....\..\clock.sta_cmp.8_slow_1200mv_85c.tdb
.....\..\clock.syn_hier_info
.....\..\clock.tiscmp.fast_1200mv_0c.ddb
.....\..\clock.tiscmp.slow_1200mv_0c.ddb
.....\..\clock.tiscmp.slow_1200mv_85c.ddb
.....\..\clock.tis_db_list.ddb
.....\..\clock.tmw_info
.....\..\logic_util_heursitic.dat
.....\..\prev_cmp_clock.qmsg
.....\simulation\modelsim

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