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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-11-01
  • Size : 60kb
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  • Author :li***
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Introduction - If you have any usage issues, please Google them yourself
FPGA control SRAM write timing source code Guifa novice understand at a glance
Packet file list
(Preview for download)


sram
....\db
....\..\sram.db_info
....\..\sram.sim.vwf
....\..\sram.sld_design_entry.sci
....\sram.asm.rpt
....\sram.done
....\sram.fit.eqn
....\sram.fit.rpt
....\sram.fit.summary
....\sram.flow.rpt
....\sram.map.eqn
....\sram.map.rpt
....\sram.map.summary
....\sram.pin
....\sram.qpf
....\sram.qsf
....\sram.qws
....\sram.sim.rpt
....\sram.tan.rpt
....\sram.tan.summary
....\sram.vhd
....\sram.vwf
....\sram_assignment_defaults.qdf
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