Design Process Design ② ① instruction format defined micro-operation ③ ④ processor division beat a detailed description of the structural design and function block diagram (score focus) a detailed description single wire connection between modules with thin lines, 2 and above with crude line and mark the number and. b. Use the arrow indicating the flow of data, signal names used in cases of functional modules shall be marked ⑤ structural design diagram and functional description (score focus) ⑥ VHDL code on connection, UCF file test instruction sequence (the meaning of each instruction) ⑦ experiments summarized in debugging and downloading problems encountered in the proce

myfpga\MCPU\MALU.vhd
......\....\MBACK.vhd
......\....\MCLK.vhd
......\....\MCPU.cmd_log
......\....\MCPU.ise
......\....\MCPU.ise_ISE_Backup
......\....\MCPU.lso
......\....\MCPU.ngc
......\....\MCPU.ngr
......\....\MCPU.prj
......\....\MCPU.stx
......\....\MCPU.syr
......\....\MCPU.vhd
......\....\MCPU.xst
......\....\MCPU_summary.html
......\....\MCPU_vhdl.prj
......\....\MCTRL.vhd
......\....\MGETIR.vhd
......\....\MMEM.vhd
......\....\MyALU.jhd
......\....\MyALU.tbw
......\....\MyALU_bencher.prj
......\....\MyBACK.jhd
......\....\MyBACK.tbw
......\....\MyCLK.jhd
......\....\MyCLK.tbw
......\....\MyCPU.jhd
......\....\MyCPU.tbw
......\....\MyCTRL.jhd
......\....\MyCTRL.tbw
......\....\MyGETIR.jhd
......\....\MyGETIR.tbw
......\....\MyMEM.jhd
......\....\MyMEM.tbw
......\....\xst\work\hdllib.ref
......\....\...\....\hdpdeps.ref
......\....\...\....\sub00\vhpl00.vho
......\....\...\....\.....\vhpl01.vho
......\....\...\....\.....\vhpl02.vho
......\....\...\....\.....\vhpl03.vho
......\....\...\....\.....\vhpl04.vho
......\....\...\....\.....\vhpl05.vho
......\....\...\....\.....\vhpl06.vho
......\....\...\....\.....\vhpl07.vho
......\....\...\....\.....\vhpl08.vho
......\....\...\....\.....\vhpl09.vho
......\....\...\....\.....\vhpl10.vho
......\....\...\....\.....\vhpl11.vho
......\....\...\....\.....\vhpl12.vho
......\....\...\....\.....\vhpl13.vho
......\....\_xmsgs\xst.xmsgs
......\QQ截图20111205201006.jpg
......\保留版\MCPU\.lso
......\......\....\cpu.xwv
......\......\....\cpu.xwv_bak
......\......\....\cpu_bencher.prj
......\......\....\isim.hdlsourcefiles
......\......\....\isim.log
......\......\....\.....tmp_save\_1
......\......\....\isimwavedata.xwv
......\......\....\MALU.prj
......\......\....\MALU.stx
......\......\....\MALU.vhd
......\......\....\MALU.xst
......\......\....\MALU_vhdl.prj
......\......\....\MBACK.vhd
......\......\....\MBACK_vhdl.prj
......\......\....\MCLK.vhd
......\......\....\MCLK_vhdl.prj
......\......\....\mcpu.bgn
......\......\....\mcpu.bit
......\......\....\MCPU.bld
......\......\....\Mcpu.cel
......\......\....\MCPU.cmd_log
......\......\....\mcpu.drc
......\......\....\MCPU.ise
......\......\....\MCPU.ise_ISE_Backup
......\......\....\MCPU.lfp
......\......\....\MCPU.lso
......\......\....\MCPU.ncd
......\......\....\MCPU.ngc
......\......\....\MCPU.ngd
......\......\....\MCPU.ngr
......\......\....\MCPU.ntrc_log
......\......\....\MCPU.pad
......\......\....\MCPU.par
......\......\....\MCPU.pcf
......\......\....\MCPU.prj
......\......\....\MCPU.stx
......\......\....\MCPU.syr
......\......\....\mcpu.twr
......\......\....\mcpu.twx
......\......\....\Mcpu.ucf
......\......\....\MCPU.unroutes
......\......\....\MCPU.ut
......\......\....\MCPU.vhd
......\......\....\MCPU.xpi
......\......\....\MCPU.xst
......\......\....\MCPU_guide.ncd
......\......\....\MCPU_map.map

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