A detailed description of the design process and problems encountered in the experiment, including:. ① ② micro-operation instruction format design definition ③ ④ processor division beat detailed description of the structural design and function block diagram (score focus) a single-wire connection between modules with a thin, two more than the number indicated by bold lines and and. b. Use the arrow indicating the flow of data, signal names used when instantiated ⑤ shall be marked on the connection of each functional module design and function block diagram and description (Ratings Key) ⑥ VHDL code, UCF file, test instruction sequence (the meaning of each instruction) experiments summarized problems encountered during commissioning and download the

lab6
....\newdata2.dat
....\newnewcpu
....\.........\alu.vhd
....\.........\bstest.ant
....\.........\bstest.fdo
....\.........\bstest.jhd
....\.........\bstest.tbw
....\.........\bstest.udo
....\.........\bstest.vhw
....\.........\bstest.xwv
....\.........\bstest.xwv_bak
....\.........\bstest_bencher.prj
....\.........\count5.vhd
....\.........\cpu.bgn
....\.........\cpu.bit
....\.........\cpu.bld
....\.........\cpu.cel
....\.........\cpu.cmd_log
....\.........\cpu.drc
....\.........\cpu.fdo
....\.........\cpu.lfp
....\.........\cpu.lso
....\.........\cpu.ncd
....\.........\cpu.ngc
....\.........\cpu.ngd
....\.........\cpu.ngr
....\.........\cpu.pad
....\.........\cpu.par
....\.........\cpu.pcf
....\.........\cpu.prj
....\.........\cpu.stx
....\.........\cpu.syr
....\.........\cpu.twr
....\.........\cpu.twx
....\.........\cpu.ucf
....\.........\cpu.udo
....\.........\cpu.unroutes
....\.........\cpu.ut
....\.........\cpu.vhd
....\.........\cpu.xpi
....\.........\cpu.xst
....\.........\cpu_guide.ncd
....\.........\cpu_map.map
....\.........\cpu_map.mrp
....\.........\cpu_map.ncd
....\.........\cpu_map.ngm
....\.........\cpu_pad.csv
....\.........\cpu_pad.txt
....\.........\cpu_prev_built.ngd
....\.........\cpu_summary.html
....\.........\cpu_summary.xml
....\.........\cpu_usage.xml
....\.........\cpu_vhdl.prj
....\.........\device_usage_statistics.html
....\.........\irctl.vhd
....\.........\memctl.vhd
....\.........\memory.vhd
....\.........\newnewcpu.ise
....\.........\newnewcpu.ise_ISE_Backup
....\.........\newnewcpu.ntrc_log
....\.........\pepExtractor.prj
....\.........\results.txt
....\.........\rewrite.vhd
....\.........\test2.jhd
....\.........\test2.tbw
....\.........\test2_bencher.prj
....\.........\testalu.ant
....\.........\testalu.fdo
....\.........\testalu.jhd
....\.........\testalu.tbw
....\.........\testalu.udo
....\.........\testalu.vhw
....\.........\testalu.xwv
....\.........\testalu.xwv_bak
....\.........\testalu_bencher.prj
....\.........\testclk.ant
....\.........\testclk.fdo
....\.........\testclk.jhd
....\.........\testclk.tbw
....\.........\testclk.udo
....\.........\testclk.xwv
....\.........\testclk.xwv_bak
....\.........\testclk_bencher.prj
....\.........\testir.ant
....\.........\testir.fdo
....\.........\testir.jhd
....\.........\testir.tbw
....\.........\testir.udo
....\.........\testir.xwv
....\.........\testir.xwv_bak
....\.........\testir_bencher.prj
....\.........\testmemctl.ant
....\.........\testmemctl.fdo
....\.........\testmemctl.jhd
....\.........\testmemctl.tbw
....\.........\testmemctl.udo
....\.........\testmemctl.xwv
....\.........\testmemctl.xwv_bak
....\.........\testmemctl_bencher.prj

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