This a counter program written in VHDL, simulation and hardware verification entirely correct, is a good example VHDL for beginners to learn.

shiyan_4
........\count_add.asm.rpt
........\count_add.done
........\count_add.eda.rpt
........\count_add.fit.rpt
........\count_add.fit.smsg
........\count_add.fit.summary
........\count_add.flow.rpt
........\count_add.map.rpt
........\count_add.map.summary
........\count_add.pin
........\count_add.pof
........\count_add.qpf
........\count_add.qsf
........\count_add.qws
........\count_add.sim.rpt
........\count_add.sof
........\count_add.tan.rpt
........\count_add.tan.summary
........\count_add.vhd
........\count_add.vwf
........\db
........\..\count_add.asm.qmsg
........\..\count_add.cbx.xml
........\..\count_add.cmp.bpm
........\..\count_add.cmp.cdb
........\..\count_add.cmp.ecobp
........\..\count_add.cmp.hdb
........\..\count_add.cmp.kpt
........\..\count_add.cmp.logdb
........\..\count_add.cmp.rdb
........\..\count_add.cmp.tdb
........\..\count_add.cmp0.ddb
........\..\count_add.cmp_merge.kpt
........\..\count_add.db_info
........\..\count_add.eco.cdb
........\..\count_add.eda.qmsg
........\..\count_add.eds_overflow
........\..\count_add.fit.qmsg
........\..\count_add.hier_info
........\..\count_add.hif
........\..\count_add.lpc.html
........\..\count_add.lpc.rdb
........\..\count_add.lpc.txt
........\..\count_add.map.bpm
........\..\count_add.map.cdb
........\..\count_add.map.ecobp
........\..\count_add.map.hdb
........\..\count_add.map.kpt
........\..\count_add.map.logdb
........\..\count_add.map.qmsg
........\..\count_add.map_bb.cdb
........\..\count_add.map_bb.hdb
........\..\count_add.map_bb.logdb
........\..\count_add.pre_map.cdb
........\..\count_add.pre_map.hdb
........\..\count_add.rtlv.hdb
........\..\count_add.rtlv_sg.cdb
........\..\count_add.rtlv_sg_swap.cdb
........\..\count_add.sgdiff.cdb
........\..\count_add.sgdiff.hdb
........\..\count_add.sim.cvwf
........\..\count_add.sim.hdb
........\..\count_add.sim.qmsg
........\..\count_add.sim.rdb
........\..\count_add.sld_design_entry.sci
........\..\count_add.sld_design_entry_dsc.sci
........\..\count_add.syn_hier_info
........\..\count_add.tan.qmsg
........\..\count_add.tis_db_list.ddb
........\..\count_add.tmw_info
........\..\count_add_global_asgn_op.abo
........\..\prev_cmp_count_add.qmsg
........\..\prev_cmp_count_add.sim.qmsg
........\..\wed.wsf
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\count_add.root_partition.cmp.atm
........\..............\...................\count_add.root_partition.cmp.dfp
........\..............\...................\count_add.root_partition.cmp.hdbx
........\..............\...................\count_add.root_partition.cmp.kpt
........\..............\...................\count_add.root_partition.cmp.logdb
........\..............\...................\count_add.root_partition.cmp.rcf
........\..............\...................\count_add.root_partition.map.atm
........\..............\...................\count_add.root_partition.map.dpi
........\..............\...................\count_add.root_partition.map.hdbx
........\..............\...................\count_add.root_partition.map.kpt
........\..............\README
........\simulation
........\..........\modelsim
........\..........\........\count_add.sft
........\..........\........\count_add.vho
........\..........\........\count_add_modelsim.xrf
........\..........\........\count_add_vhd.sdo

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