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shiyan_2_1

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-11-08
  • Size : 316kb
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  • Author :w****
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Introduction - If you have any usage issues, please Google them yourself
This a write VHDL data selector, correct simulation and verification, is a good example for beginners.
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shiyan_2_1
..........\db
..........\..\muxk.asm.qmsg
..........\..\muxk.asm_labs.ddb
..........\..\muxk.cbx.xml
..........\..\muxk.cmp.bpm
..........\..\muxk.cmp.cdb
..........\..\muxk.cmp.ecobp
..........\..\muxk.cmp.hdb
..........\..\muxk.cmp.kpt
..........\..\muxk.cmp.logdb
..........\..\muxk.cmp.rdb
..........\..\muxk.cmp.tdb
..........\..\muxk.cmp0.ddb
..........\..\muxk.cmp_merge.kpt
..........\..\muxk.db_info
..........\..\muxk.eco.cdb
..........\..\muxk.eda.qmsg
..........\..\muxk.eds_overflow
..........\..\muxk.fit.qmsg
..........\..\muxk.hier_info
..........\..\muxk.hif
..........\..\muxk.lpc.html
..........\..\muxk.lpc.rdb
..........\..\muxk.lpc.txt
..........\..\muxk.map.bpm
..........\..\muxk.map.cdb
..........\..\muxk.map.ecobp
..........\..\muxk.map.hdb
..........\..\muxk.map.kpt
..........\..\muxk.map.logdb
..........\..\muxk.map.qmsg
..........\..\muxk.map_bb.cdb
..........\..\muxk.map_bb.hdb
..........\..\muxk.map_bb.logdb
..........\..\muxk.pre_map.cdb
..........\..\muxk.pre_map.hdb
..........\..\muxk.rtlv.hdb
..........\..\muxk.rtlv_sg.cdb
..........\..\muxk.rtlv_sg_swap.cdb
..........\..\muxk.sgdiff.cdb
..........\..\muxk.sgdiff.hdb
..........\..\muxk.sim.cvwf
..........\..\muxk.sim.hdb
..........\..\muxk.sim.qmsg
..........\..\muxk.sim.rdb
..........\..\muxk.sld_design_entry.sci
..........\..\muxk.sld_design_entry_dsc.sci
..........\..\muxk.syn_hier_info
..........\..\muxk.tan.qmsg
..........\..\muxk.tis_db_list.ddb
..........\..\muxk.tmw_info
..........\..\muxk_global_asgn_op.abo
..........\..\prev_cmp_muxk.asm.qmsg
..........\..\prev_cmp_muxk.eda.qmsg
..........\..\prev_cmp_muxk.fit.qmsg
..........\..\prev_cmp_muxk.map.qmsg
..........\..\prev_cmp_muxk.qmsg
..........\..\prev_cmp_muxk.sim.qmsg
..........\..\prev_cmp_muxk.tan.qmsg
..........\..\wed.wsf
..........\incremental_db
..........\..............\compiled_partitions
..........\..............\...................\muxk.root_partition.cmp.atm
..........\..............\...................\muxk.root_partition.cmp.dfp
..........\..............\...................\muxk.root_partition.cmp.hdbx
..........\..............\...................\muxk.root_partition.cmp.kpt
..........\..............\...................\muxk.root_partition.cmp.logdb
..........\..............\...................\muxk.root_partition.cmp.rcf
..........\..............\...................\muxk.root_partition.map.atm
..........\..............\...................\muxk.root_partition.map.dpi
..........\..............\...................\muxk.root_partition.map.hdbx
..........\..............\...................\muxk.root_partition.map.kpt
..........\..............\README
..........\mux21a.vhd
..........\mux21a.vhd.bak
..........\muxk.asm.rpt
..........\muxk.done
..........\muxk.eda.rpt
..........\muxk.fit.rpt
..........\muxk.fit.smsg
..........\muxk.fit.summary
..........\muxk.flow.rpt
..........\muxk.map.rpt
..........\muxk.map.summary
..........\muxk.pin
..........\muxk.pof
..........\muxk.qpf
..........\muxk.qsf
..........\muxk.qws
..........\muxk.sim.rpt
..........\muxk.sof
..........\muxk.tan.rpt
..........\muxk.tan.summary
..........\muxk.vhd
..........\muxk.vwf
..........\simulation
..........\..........\modelsim
..........\..........\........\muxk.sft
..........\..........\........\muxk.vho
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