FPGA based state machine routine design. Using Mearly type state machine. With this status, and the design process to become familiar with the design method in the state machine in Quartus

mearly\addrcompiler_47.bsf
......\addrcompiler_47.vhd
......\addrcompiler_47.vhd.bak
......\Block1.bdf
......\db\logic_util_heursitic.dat
......\..\mux_joc.tdf
......\..\prev_cmp_ram_controller.map.qmsg
......\..\prev_cmp_ram_controller.qmsg
......\..\ram_controller.cbx.xml
......\..\ram_controller.cmp.rdb
......\..\ram_controller.cmp_merge.kpt
......\..\ram_controller.db_info
......\..\ram_controller.eco.cdb
......\..\ram_controller.eds_overflow
......\..\ram_controller.fnsim.cdb
......\..\ram_controller.fnsim.hdb
......\..\ram_controller.fnsim.qmsg
......\..\ram_controller.hier_info
......\..\ram_controller.hif
......\..\ram_controller.lpc.html
......\..\ram_controller.lpc.rdb
......\..\ram_controller.lpc.txt
......\..\ram_controller.map.bpm
......\..\ram_controller.map.cdb
......\..\ram_controller.map.ecobp
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......\..\ram_controller.map.kpt
......\..\ram_controller.map.logdb
......\..\ram_controller.map.qmsg
......\..\ram_controller.map_bb.cdb
......\..\ram_controller.map_bb.hdb
......\..\ram_controller.map_bb.logdb
......\..\ram_controller.pre_map.cdb
......\..\ram_controller.pre_map.hdb
......\..\ram_controller.rtlv.hdb
......\..\ram_controller.rtlv_sg.cdb
......\..\ram_controller.rtlv_sg_swap.cdb
......\..\ram_controller.sgdiff.cdb
......\..\ram_controller.sgdiff.hdb
......\..\ram_controller.sim.cvwf
......\..\ram_controller.sim.hdb
......\..\ram_controller.sim.qmsg
......\..\ram_controller.sim.rdb
......\..\ram_controller.simfam
......\..\ram_controller.sld_design_entry.sci
......\..\ram_controller.sld_design_entry_dsc.sci
......\..\ram_controller.smart_action.txt
......\..\ram_controller.smp_dump.txt
......\..\ram_controller.syn_hier_info
......\..\ram_controller.tis_db_list.ddb
......\..\wed.wsf
......\incremental_db\compiled_partitions\ram_controller.root_partition.map.cdb
......\..............\...................\ram_controller.root_partition.map.dpi
......\..............\...................\ram_controller.root_partition.map.hdb
......\..............\...................\ram_controller.root_partition.map.kpt
......\..............\README
......\ram_controller.bsf
......\ram_controller.done
......\ram_controller.flow.rpt
......\ram_controller.map.rpt
......\ram_controller.map.summary
......\ram_controller.qpf
......\ram_controller.qsf
......\ram_controller.qws
......\ram_controller.sim.rpt
......\ram_controller.vhd
......\ram_controller.vhd.bak
......\ram_controller.vwf
......\incremental_db\compiled_partitions
......\db
......\incremental_db
mearly

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