FPGA-based digital control procedures. This program is designed to be familiar with VHDL programming design methods and hardware control methods. After this program download, plus two digital high count, the lower two counts down, press the reset is cleared.

seg47_2c5\addcont.bsf
.........\addcont.vhd
.........\bin27seg.bsf
.........\bin27seg.vhd
.........\db\cntr_bgd.tdf
.........\..\cntr_tnd.tdf
.........\..\seg47.db_info
.........\..\seg47.eco.cdb
.........\..\seg47.sld_design_entry.sci
.........\lpm_counter0.bsf
.........\lpm_counter0.cmp
.........\lpm_counter0.vhd
.........\lpm_counter0_wave0.jpg
.........\lpm_counter0_waveforms.html
.........\lpm_counter1.bsf
.........\lpm_counter1.cmp
.........\lpm_counter1.vhd
.........\lpm_counter1_wave0.jpg
.........\lpm_counter1_waveforms.html
.........\seg47.asm.rpt
.........\seg47.bdf
.........\seg47.cdf
.........\seg47.done
.........\seg47.fit.eqn
.........\seg47.fit.rpt
.........\seg47.fit.summary
.........\seg47.flow.rpt
.........\seg47.map.eqn
.........\seg47.map.rpt
.........\seg47.map.summary
.........\seg47.pin
.........\seg47.pof
.........\seg47.qpf
.........\seg47.qsf
.........\seg47.qws
.........\seg47.sof
.........\seg47.tan.rpt
.........\seg47.tan.summary
.........\seg47_assignment_defaults.qdf
.........\segmain.bsf
.........\segmain.vhd
.........\setup.tcl
.........\sscom.ini
.........\subcont.bsf
.........\subcont.vhd
.........\db
seg47_2c5

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