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Frame-synchronization

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-11-16
  • Size : 4kb
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  • Author :刘***
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Frame synchronization state machine is mainly to overcome all kinds of unexpected situations that may occur in communications, including loss of signal, the communication channel error caused by the interruption, try to maintain a normal communicate. When the system starts, synchronous state machine is out of gait, and continues to search for a valid input signal synchronous mode (" 10011011" ), as soon as it finds a valid synchronous mode, enter the pre-synchronization state in pre-synchronization state also can not completely determine the start position of the current frame is found (as determined by the synchronization mode position) are correct, but also the need to continue to check whether the two separated one frame length (256 clocks) after the location is still valid in the synchronous mode, if present, then synchronous state machine will enter the synchronized state, otherwise it will return loss gait continue to search for the next valid synchronization pattern in
Packet file list
(Preview for download)


scrambler.v
Final.v
final_tb.v
Frame_Synm.v
FrameDataCheck.v
FrameTrans.v
FSYNM_tb.v
InputMode.v
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