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digital-clock

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2014-11-19
  • Size : 283kb
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  • Author :d***
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FPGA digital clock
Packet file list
(Preview for download)


数字钟1
.......\多功能数字电子钟_VHDL.doc
.......\数字逻辑课程设计.doc
.......\源文件
.......\......\bell.sof
.......\......\bell.vhd
.......\......\bridge.sof
.......\......\bridge.vhd
.......\......\comp.sof
.......\......\comp.vhd
.......\......\controller.scf
.......\......\controller.sof
.......\......\controller.vhd
.......\......\count_16.sof
.......\......\count_8.sof
.......\......\count_8.vhd
.......\......\decode8.sof
.......\......\decode8.vhd
.......\......\dshi.vhd
.......\......\dx.sof
.......\......\fenp.sof
.......\......\fenpin.scf
.......\......\fenpin.vhd
.......\......\h24.scf
.......\......\h24.vhd
.......\......\jishi.vhd
.......\......\kong.sof
.......\......\kong.vhd
.......\......\m60.scf
.......\......\m60.sof
.......\......\m60.vhd
.......\......\mux2.vhd
.......\......\mux2_1.scf
.......\......\mux2_1.sof
.......\......\mux2_1.vhd
.......\......\mux8_1.sof
.......\......\mux8_1.vhd
.......\......\s60.scf
.......\......\s60.sof
.......\......\s60.vhd
.......\......\showconl.sof
.......\......\showconl.vhd
.......\......\shuzizhong.gdf
.......\......\shuzizhong.sof
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