VerilogHDLPIC16c - VerilogHDL implementation of PIC16c5x

Testbench
.........\TB_mux_alu_b.v
.........\TB_alu_op_gen.v
.........\TB_alu_top.v
.........\TB_instruction_decoder.v
.........\TB_instruction_decoder_top.v
.........\TB_mux_alu_a.v
.........\TB_alu_op.v
.........\TB_pic16c5x.v
.........\TB_pic16c5x.v~
.........\TB_reg_fsr.v
.........\TB_reg_general.v
.........\TB_reg_top.v
source
......\rom_7.dat
......\rom.dat
......\alu_op_gen.v
......\reg_general.v
......\alu_op.v
......\rom_8.dat
......\alu_top.v
......\rom_6.dat
......\rom_6_org.dat
......\instruction_decoder.v
......\instruction_decoder_top.v
......\instruction_reg.v
......\mux_alu_a.v
......\mux_alu_b.v
......\rom_1.dat
......\mux_fwe.v
......\pic16c5x.v
......\mux_status_write.v
......\program_counter.v
......\reg_fsr.v
......\reg_io.v
......\reg_mux_f.v
......\reg_status.v
......\reg_mux_w.v
......\reg_top.v
......\reg_w.v
synthesis
.........\exemplar.log
.........\pic16c5x_project.lsp
.........\pic16c5x_project.scr
.........\pic16c5x_project.xdb
.........\report

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