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09_uart2

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-12-03
  • Size : 103kb
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  • Author :陈***
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Introduction - If you have any usage issues, please Google them yourself
FPGA UART
Packet file list
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09_uart2
........\db
........\..\logic_util_heursitic.dat
........\..\my_uart_top.db_info
........\..\my_uart_top.sld_design_entry.sci
........\..\my_uart_top_global_asgn_op.abo
........\..\prev_cmp_my_uart_top.asm.qmsg
........\..\prev_cmp_my_uart_top.fit.qmsg
........\..\prev_cmp_my_uart_top.map.qmsg
........\..\prev_cmp_my_uart_top.qmsg
........\..\prev_cmp_my_uart_top.tan.qmsg
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\my_uart_top.db_info
........\..............\...................\my_uart_top.root_partition.cmp.dfp
........\..............\...................\my_uart_top.root_partition.cmp.kpt
........\..............\...................\my_uart_top.root_partition.cmp.logdb
........\..............\...................\my_uart_top.root_partition.map.dpi
........\..............\...................\my_uart_top.root_partition.map.kpt
........\..............\README
........\my_uart_rx.v
........\my_uart_rx.v.bak
........\my_uart_top.asm.rpt
........\my_uart_top.cdf
........\my_uart_top.done
........\my_uart_top.fit.rpt
........\my_uart_top.fit.smsg
........\my_uart_top.fit.summary
........\my_uart_top.flow.rpt
........\my_uart_top.jpg
........\my_uart_top.map.rpt
........\my_uart_top.map.smsg
........\my_uart_top.map.summary
........\my_uart_top.pin
........\my_uart_top.pof
........\my_uart_top.qpf
........\my_uart_top.qsf
........\my_uart_top.qws
........\my_uart_top.sta.rpt
........\my_uart_top.sta.summary
........\my_uart_top.tan.rpt
........\my_uart_top.tan.summary
........\my_uart_top.v
........\my_uart_top.v.bak
........\my_uart_top_assignment_defaults.qdf
........\my_uart_tx.v
........\my_uart_tx.v.bak
........\speed_select.v
........\speed_select.v.bak
........\说明.txt
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