100MHZ clock signal through a divider to get 1HZ signal, and then input to the three counters, the output of the counter displayed on the corresponding LED lights on the FPGA. The program consists of four main parts: the test file, the top-level file, split screen modules and counter module.

counter\counter3b.v
.......\div_clk.v
.......\test_counter.v
.......\top.v
counter

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