Hot Search : Source embeded web remote control p2p game More...
Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog

simple_CPU_VHDL

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2014-12-09
  • Size : 2.42mb
  • Downloaded :0次
  • Author :wo***
  • About : Nobody
  • PS : If download it fails, try it again. Download again for free!
Download1 Download2
Don't use download software fo downloading.
If download fail,Try it again for free.
Introduction - If you have any usage issues, please Google them yourself
-Simple CPU design of the VHDL code and VHDL design process cpu
Packet file list
(Preview for download)


实验7.1——基本CPU设计\实践报告.doc
......................\cpu\alu.bsf
......................\...\alu.vhd
......................\...\ar.bsf
......................\...\ar.vhd
......................\...\bus_dir.bsf
......................\...\bus_dir.vhd
......................\...\bus_mux.bsf
......................\...\bus_mux.vhd
......................\...\cmp_state.ini
......................\...\controller.bsf
......................\...\controller.vhd
......................\...\cpu0.asm.rpt
......................\...\cpu0.bdf
......................\...\cpu0.done
......................\...\cpu0.fit.eqn
......................\...\cpu0.fit.rpt
......................\...\cpu0.fit.summary
......................\...\cpu0.flow.rpt
......................\...\cpu0.map.eqn
......................\...\cpu0.map.rpt
......................\...\cpu0.map.summary
......................\...\cpu0.pin
......................\...\cpu0.pof
......................\...\cpu0.qpf
......................\...\cpu0.qsf
......................\...\cpu0.qws
......................\...\cpu0.sof
......................\...\cpu0.tan.rpt
......................\...\cpu0.tan.summary
......................\...\cpu0_assignment_defaults.qdf
......................\...\flag_reg.bsf
......................\...\flag_reg.vhd
......................\...\ir.bsf
......................\...\ir.vhd
......................\...\pc.bsf
......................\...\pc.vhd
......................\...\reg.bsf
......................\...\reg.vhd
......................\...\reg_mux.bsf
......................\...\reg_mux.vhd
......................\...\reg_out.bsf
......................\...\reg_out.vhd
......................\...\reg_test.bsf
......................\...\reg_test.vhd
......................\...\reg_testa.bsf
......................\...\reg_testa.vhd
......................\...\t1.bsf
......................\...\t1.vhd
......................\...\t2.bsf
......................\...\t2.vhd
......................\...\t3.bsf
......................\...\t3.vhd
......................\...\timer.bsf
......................\...\timer.vhd
......................\...\db\add_sub_kjh.tdf
......................\...\..\add_sub_ljh.tdf
......................\...\..\cpu0.eco.cdb
......................\...\..\cpu0.cbx.xml
......................\...\..\cpu0.sld_design_entry.sci
......................\...\..\cpu0.map.qmsg
......................\...\..\cpu0.pre_map.hdb
......................\...\..\cpu0.cmp.rdb
......................\...\..\cpu0.db_info
......................\...\..\cpu0.pre_map.cdb
......................\...\..\cpu0.hier_info
......................\...\..\cpu0.hif
......................\...\..\cpu0.rtlv.hdb
......................\...\..\cpu0.rtlv_sg.cdb
......................\...\..\cpu0.rtlv_sg_swap.cdb
......................\...\..\cpu0.sld_design_entry_dsc.sci
......................\...\..\cpu0.psp
......................\...\..\cpu0.fit.qmsg
......................\...\..\cpu0.sgdiff.cdb
......................\...\..\cpu0.map.hdb
......................\...\..\cpu0.sgdiff.hdb
......................\...\..\cpu0.map.cdb
......................\...\..\cpu0.cmp0.ddb
......................\...\..\cpu0.cmp.cdb
......................\...\..\cpu0.cmp.hdb
......................\...\..\cpu0.asm.qmsg
......................\...\..\cpu0.smp_dump.txt
......................\...\..\cpu0.syn_hier_info
......................\...\..\cpu0.tan.qmsg
......................\...\..\cpu0_cmp.qrpt
......................\...\..\cpu0.signalprobe.cdb
......................\...\..\cpu0.cmp.tdb
......................\...\cpu0.cdf
......................\.onfig&samples\cpu.txt
......................\..............\ex1.txt
......................\..............\ex2.txt
......................\..............\ex3.txt
......................\..............\123.txt
......................\.pu\db
......................\cpu
......................\config&samples
实验7.1——基本CPU设计
Related instructions
  • We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
  • The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
  • Please use Winrar for decompression tools
  • If download fail, Try it againg or Feedback to us.
  • If downloaded content did not match the introduction, Feedback to us,Confirm and will be refund.
  • Before downloading, you can inquire through the uploaded person information

Nothing.

Post Comment
*Quick comment Recommend Not bad Password Unclear description Not source
Lost files Unable to decompress Bad
*Content :
*Captcha :
CodeBus is one of the largest source code repositories on the Internet!
Contact us :
1999-2046 CodeBus All Rights Reserved.