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38-always

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-12-10
  • Size : 119kb
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  • Author :Dr.S****
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Introduction - If you have any usage issues, please Google them yourself
This program uses the always statement to realize 3-8 decoder function, simulation waveform is right.
Packet file list
(Preview for download)


38 always
.........\D3_8s.asm.rpt
.........\D3_8s.done
.........\D3_8s.fit.rpt
.........\D3_8s.fit.smsg
.........\D3_8s.fit.summary
.........\D3_8s.flow.rpt
.........\D3_8s.map.rpt
.........\D3_8s.map.smsg
.........\D3_8s.map.summary
.........\D3_8s.pin
.........\D3_8s.pof
.........\D3_8s.qpf
.........\D3_8s.qsf
.........\D3_8s.qws
.........\D3_8s.sim.rpt
.........\D3_8s.sof
.........\D3_8s.tan.rpt
.........\D3_8s.tan.summary
.........\D3_8s.v
.........\D3_8s.vwf
.........\db
.........\..\D3_8s.asm.qmsg
.........\..\D3_8s.cbx.xml
.........\..\D3_8s.cmp.cdb
.........\..\D3_8s.cmp.hdb
.........\..\D3_8s.cmp.kpt
.........\..\D3_8s.cmp.logdb
.........\..\D3_8s.cmp.rdb
.........\..\D3_8s.cmp.tdb
.........\..\D3_8s.cmp0.ddb
.........\..\D3_8s.db_info
.........\..\D3_8s.dbp
.........\..\D3_8s.eco.cdb
.........\..\D3_8s.eds_overflow
.........\..\D3_8s.fit.qmsg
.........\..\D3_8s.fnsim.cdb
.........\..\D3_8s.fnsim.hdb
.........\..\D3_8s.fnsim.qmsg
.........\..\D3_8s.hier_info
.........\..\D3_8s.hif
.........\..\D3_8s.map.cdb
.........\..\D3_8s.map.hdb
.........\..\D3_8s.map.logdb
.........\..\D3_8s.map.qmsg
.........\..\D3_8s.pre_map.cdb
.........\..\D3_8s.pre_map.hdb
.........\..\D3_8s.psp
.........\..\D3_8s.rtlv.hdb
.........\..\D3_8s.rtlv_sg.cdb
.........\..\D3_8s.rtlv_sg_swap.cdb
.........\..\D3_8s.sgdiff.cdb
.........\..\D3_8s.sgdiff.hdb
.........\..\D3_8s.signalprobe.cdb
.........\..\D3_8s.sim.hdb
.........\..\D3_8s.sim.qmsg
.........\..\D3_8s.sim.rdb
.........\..\D3_8s.sim.vwf
.........\..\D3_8s.sld_design_entry.sci
.........\..\D3_8s.sld_design_entry_dsc.sci
.........\..\D3_8s.syn_hier_info
.........\..\D3_8s.tan.qmsg
.........\..\wed.zsf
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