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Mini-Risc-core

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-12-11
  • Size : 101kb
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  • Author :金****
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Introduction - If you have any usage issues, please Google them yourself
This a Mini-RISC CPU/Microcontroller that is mostly compatible with the PIC 16C57 Microchip.
Packet file list
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Mini-Risc core
..............\CVS
..............\...\Entries
..............\...\Repository
..............\...\Root
..............\README.TXT
..............\SCODE
..............\.....\CVS
..............\.....\...\Entries
..............\.....\...\Repository
..............\.....\...\Root
..............\.....\HEX2V.C
..............\.....\RF1.ASM
..............\.....\RF1.ROM
..............\.....\RF2.ASM
..............\.....\RF2.ROM
..............\.....\RF3.ASM
..............\.....\RF3.ROM
..............\.....\SANITY1.ASM
..............\.....\SANITY1.ROM
..............\.....\SANITY2.ASM
..............\.....\SANITY2.ROM
..............\.....\TMR_WDT.ASM
..............\.....\TMR_WDT.ROM
..............\SIM
..............\...\CVS
..............\...\...\Entries
..............\...\...\Repository
..............\...\...\Root
..............\...\RUN
..............\VERILOG
..............\.......\CORE
..............\.......\....\ALU.V
..............\.......\....\CVS
..............\.......\....\...\Entries
..............\.......\....\...\Repository
..............\.......\....\...\Root
..............\.......\....\presclr_wdt.v
..............\.......\....\primitives.v
..............\.......\....\primitives_xilinx.v
..............\.......\....\register_file.v
..............\.......\....\risc_core.v
..............\.......\....\risc_core_top.v
..............\.......\CVS
..............\.......\...\Entries
..............\.......\...\Repository
..............\.......\...\Root
..............\.......\testbench
..............\.......\.........\CVS
..............\.......\.........\...\Entries
..............\.......\.........\...\Repository
..............\.......\.........\...\Root
..............\.......\.........\PROG_MEM.V
..............\.......\.........\TEST.V
..............\xilinx_primitives
..............\.................\xilinx_add_sub8_co.edn
..............\.................\xilinx_cmp8_eq.edn
..............\.................\xilinx_inc11.edn
..............\.................\xilinx_inc8.edn
..............\.................\xilinx_mux2_11.edn
..............\.................\xilinx_mux2_7.edn
..............\.................\xilinx_mux2_8.edn
..............\.................\xilinx_mux4_8.edn
..............\.................\xilinx_mux8_1.edn
..............\.................\xilinx_mux8_8.edn
..............\.................\xilinx_ssram_128x8.edn
..............\.................\xilinx_ssram_128x8.mif
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