This report investigates the power consumption of digital arithmetic circuits for use in the design and implementation of a 15-tap programmable Finite Impulse Response (FIR) filter.

Low Power FIR Filter
....................\16AdderBalanced.vhd
....................\16ADDERBALANCED_old.vhd
....................\1BITADDER.VHD
....................\1BITPFA.VHD
....................\4BITCLA.VHD
....................\8BITREG3.VHD
....................\ADDERDELAY.VHD
....................\BalancedMult.VHD
....................\CoefficientTest.vhd
....................\COMB0.VHD
....................\COMB1.VHD
....................\COMB2.VHD
....................\COMB3.VHD
....................\COUNTER.VHD
....................\DelayBlock.VHD
....................\EnableALL3.vhd
....................\FinalBalancedFIR.vhd
....................\FinalBalancedFIR2.vhd
....................\FIRLowPowerConsiderations.doc
....................\HC.VHD
....................\MCELL11.VHD
....................\MCELL21.VHD
....................\MCELL210.VHD
....................\MCELL212.VHD
....................\MCELL214.VHD
....................\MCELL21_1.VHD
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....................\MCELL61.VHD
....................\MCELL71.VHD
....................\MCELLnone.VHD
....................\NEWSLICE.VHD
....................\ORBLOCK.VHD
....................\ORCOMP.VHD
....................\ORPART2.VHD
....................\SINETEST.VHD
....................\SineTest4KSample1.1Ksignal.vhd
....................\SineTest4KSample1Ksignal.vhd
....................\SineTest4KSample500Hzsignal.vhd
....................\sinetesttenK.vhd
....................\TAPADDER.VHD
....................\TAPCONTROL.VHD
....................\tb_balancedtest.vhd
....................\TTLDTYPE.VHD
....................\ttlNodelays.vhd
....................\XORBLOCK.VHD

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