Synthesis based on direct sequence vhdl language s ynthesis based on direct sequence vhdl language

DDS\counter_bus_mux.qip
...\db\zy_dds.db_info
...\..\zy_dds.sld_design_entry.sci
...\dds.vhd
...\greybox_tmp\cbx_args.txt
...\pll.bsf
...\pll.ppf
...\pll.qip
...\pll.v
...\pll_bb.v
...\simple_counter.bsf
...\Verilog1.v
...\Verilog1.v.bak
...\zy_dds.bdf
...\zy_dds.done
...\zy_dds.qpf
...\zy_dds.qsf
...\zy_dds.vhd
...\zy_dds.vhd.bak
...\db
...\greybox_tmp
DDS

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