Altera cyclone Ⅳ EP4CE30F23C8N based platform. Includes sync structure fifo2 principle, design and source code. Can be directly admitted to the development board, containing modelsim waveform, easy to use simulation

sync_fifo2
..........\db
..........\..\altsyncram_t8i1.tdf
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_sync_fifo.qmsg
..........\..\sync_fifo.amm.cdb
..........\..\sync_fifo.asm.qmsg
..........\..\sync_fifo.asm.rdb
..........\..\sync_fifo.asm_labs.ddb
..........\..\sync_fifo.cbx.xml
..........\..\sync_fifo.cmp.bpm
..........\..\sync_fifo.cmp.cdb
..........\..\sync_fifo.cmp.hdb
..........\..\sync_fifo.cmp.kpt
..........\..\sync_fifo.cmp.logdb
..........\..\sync_fifo.cmp.rdb
..........\..\sync_fifo.cmp_merge.kpt
..........\..\sync_fifo.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
..........\..\sync_fifo.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
..........\..\sync_fifo.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
..........\..\sync_fifo.db_info
..........\..\sync_fifo.eda.qmsg
..........\..\sync_fifo.fit.qmsg
..........\..\sync_fifo.hier_info
..........\..\sync_fifo.hif
..........\..\sync_fifo.idb.cdb
..........\..\sync_fifo.lpc.html
..........\..\sync_fifo.lpc.rdb
..........\..\sync_fifo.lpc.txt
..........\..\sync_fifo.map.bpm
..........\..\sync_fifo.map.cdb
..........\..\sync_fifo.map.hdb
..........\..\sync_fifo.map.kpt
..........\..\sync_fifo.map.logdb
..........\..\sync_fifo.map.qmsg
..........\..\sync_fifo.map_bb.cdb
..........\..\sync_fifo.map_bb.hdb
..........\..\sync_fifo.map_bb.logdb
..........\..\sync_fifo.pre_map.cdb
..........\..\sync_fifo.pre_map.hdb
..........\..\sync_fifo.rtlv.hdb
..........\..\sync_fifo.rtlv_sg.cdb
..........\..\sync_fifo.rtlv_sg_swap.cdb
..........\..\sync_fifo.sgdiff.cdb
..........\..\sync_fifo.sgdiff.hdb
..........\..\sync_fifo.sld_design_entry.sci
..........\..\sync_fifo.sld_design_entry_dsc.sci
..........\..\sync_fifo.smart_action.txt
..........\..\sync_fifo.sta.qmsg
..........\..\sync_fifo.sta.rdb
..........\..\sync_fifo.sta_cmp.8_slow_1200mv_85c.tdb
..........\..\sync_fifo.syn_hier_info
..........\..\sync_fifo.tiscmp.fastest_slow_1200mv_0c.ddb
..........\..\sync_fifo.tiscmp.fastest_slow_1200mv_85c.ddb
..........\..\sync_fifo.tiscmp.fast_1200mv_0c.ddb
..........\..\sync_fifo.tiscmp.slow_1200mv_0c.ddb
..........\..\sync_fifo.tiscmp.slow_1200mv_85c.ddb
..........\..\sync_fifo.tis_db_list.ddb
..........\..\sync_fifo.tmw_info
..........\incremental_db
..........\..............\compiled_partitions
..........\..............\...................\sync_fifo.db_info
..........\..............\...................\sync_fifo.root_partition.cmp.cdb
..........\..............\...................\sync_fifo.root_partition.cmp.dfp
..........\..............\...................\sync_fifo.root_partition.cmp.hdb
..........\..............\...................\sync_fifo.root_partition.cmp.kpt
..........\..............\...................\sync_fifo.root_partition.cmp.logdb
..........\..............\...................\sync_fifo.root_partition.cmp.rcfdb
..........\..............\...................\sync_fifo.root_partition.map.cdb
..........\..............\...................\sync_fifo.root_partition.map.dpi
..........\..............\...................\sync_fifo.root_partition.map.hbdb.cdb
..........\..............\...................\sync_fifo.root_partition.map.hbdb.hb_info
..........\..............\...................\sync_fifo.root_partition.map.hbdb.hdb
..........\..............\...................\sync_fifo.root_partition.map.hbdb.sig
..........\..............\...................\sync_fifo.root_partition.map.hdb
..........\..............\...................\sync_fifo.root_partition.map.kpt
..........\..............\README
..........\modelsim
..........\........\fifo.v
..........\........\fifo.v.bak
..........\........\sync_fifo.cr.mti
..........\........\sync_fifo.mpf
..........\........\vsim.wlf
..........\........\work
..........\........\....\sync_fifo
..........\........\....\.........\verilog.asm
..........\........\....\.........\_primary.dat
..........\........\....\.........\_primary.vhd
..........\........\....\sync_fifo_vlg_tst
..........\........\....\.................\verilog.asm
..........\........\....\.................\_primary.dat
..........\.......

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