RS encoder design, Verilog implementation.

RS编码器
........\mul_encode.vhd
........\mula_0.v
........\mula_1.v
........\mula_10.v
........\mula_11.v
........\mula_12.v
........\mula_13.v
........\mula_14.v
........\mula_15.v
........\mula_16.v
........\mula_17.v
........\mula_18.v
........\mula_2.v
........\mula_21.v
........\mula_22.v
........\mula_25.v
........\mula_3.v
........\mula_31.v
........\mula_32.v
........\mula_35.v
........\mula_38.v
........\mula_4.v
........\mula_45.v
........\mula_48.v
........\mula_5.v
........\mula_51.v
........\mula_59.v
........\mula_6.v
........\mula_61.v
........\mula_7.v
........\mula_8.v
........\mula_9.v
........\rscode.v
........\rscode.vhd
........\rscode.vwf
........\rstestbench.vhd
........\testbenchmul.vhd
........\testbenchmul_encode.vhd

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