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ep1c12_2_led_water

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-12-24
  • Size : 53kb
  • Downloaded :0次
  • Author :张***
  • About : Nobody
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Describe a led lamp design, water can check the quality of the crystals check minimum system is working correctly
Packet file list
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ep1c12_2_led_water\cmp_state.ini
..................\db\led_water.db_info
..................\..\led_water.eco.cdb
..................\..\led_water.sld_design_entry.sci
..................\int_div.bsf
..................\int_div.v
..................\ledwater.bsf
..................\ledwater.v
..................\led_water.asm.rpt
..................\led_water.bdf
..................\led_water.cdf
..................\led_water.done
..................\led_water.fit.eqn
..................\led_water.fit.rpt
..................\led_water.fit.summary
..................\led_water.flow.rpt
..................\led_water.map.eqn
..................\led_water.map.rpt
..................\led_water.map.summary
..................\led_water.pin
..................\led_water.pof
..................\led_water.qpf
..................\led_water.qsf
..................\led_water.qws
..................\led_water.sof
..................\led_water.tan.rpt
..................\led_water.tan.summary
..................\led_water_assignment_defaults.qdf
..................\_desktop.ini
..................\db
ep1c12_2_led_water
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