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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-01-05
  • Size : 319kb
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  • Author :H*****
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Introduction - If you have any usage issues, please Google them yourself
Single-cycle CPU, to achieve some simple instruction, simulation confirm feasible
Packet file list
(Preview for download)


CPU
...\.lso
...\ANDcomponent.v
...\ANDcomponent_envsettings.html
...\ANDcomponent_summary.html
...\Addr.v
...\AddrImm.v
...\Addr_Jump.v
...\CPU.cmd_log
...\CPU.gise
...\CPU.lso
...\CPU.prj
...\CPU.stx
...\CPU.syr
...\CPU.v
...\CPU.xise
...\CPU.xst
...\CPU_TF.v
...\CPU_TF_beh.prj
...\CPU_TF_stx_beh.prj
...\CPU_beh.prj
...\CPU_envsettings.html
...\CPU_stx_beh.prj
...\CPU_summary.html
...\CPU_xst.xrpt
...\Control.v
...\Data_memory.v
...\Extend.v
...\GetCode.prj
...\GetCode.stx
...\GetCode.v
...\GetCode.xst
...\GetCode_isim_beh1.wdb
...\Init.v
...\MIPS32_ALU.v
...\MIPS_SHIFT.v
...\MUX32_2TO1.v
...\MUX5_2TO1.v
...\ORcomponent.v
...\PC.v
...\Register.v
...\Shift21.v
...\Shift22.v
...\_xmsgs
...\......\pn_parser.xmsgs
...\......\xst.xmsgs
...\addr_2TO1.v
...\addr_2TO1_stx_beh.prj
...\cMem.v
...\cMem_stx_beh.prj
...\cacheDFFE_tf.v
...\cacheFZ0.v
...\cacheFZ0_beh.prj
...\cacheFZ0_isim_beh.exe
...\cacheFZ0_isim_beh.wdb
...\cache_counter.prj
...\cache_counter.stx
...\cache_counter.v
...\cache_counter.xst
...\cache_counter_stx_beh.prj
...\cache_mem.prj
...\cache_mem.stx
...\cache_mem.v
...\cache_mem.xst
...\cache_mem_stx_beh.prj
...\cache_table.prj
...\cache_table.stx
...\cache_table.v
...\cache_table.xst
...\cache_table_beh.prj
...\cache_table_isim_beh.wdb
...\cache_table_stx_beh.prj
...\cache_testcase.v
...\cache_testcase_stx_beh.prj
...\cache_top.prj
...\cache_top.stx
...\cache_top.v
...\cache_top.xst
...\cache_top_beh.prj
...\cache_top_stx_beh.prj
...\cache_top_summary.html
...\cache_top_tf.v
...\fuse.log
...\fuse.xmsgs
...\fuseRelaunch.cmd
...\ipcore_dir
...\iseconfig
...\.........\CPU.projectmgr
...\.........\CPU.xreport
...\.........\cache_top.xreport
...\isim
...\....\cacheFZ0_isim_beh.exe.sim
...\....\.........................\ISimEngine-DesignHierarchy.dbg
...\....\.........................\cacheFZ0_isim_beh.exe
...\....\.........................\isimcrash.log
...\....\.........................\isimkernel.log
...\....\.........................\netId.dat
...\....\.........................\tmp_save
...\....\.........................\........\_1
...\....\.........................\work
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