Introduction - If you have any usage issues, please Google them yourself
Pipeline structure is very complicated in the case of using the logic, through the sub-stack, to a complex logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal and increase the frequency. The most vivid example is the bit width larger adder. To a complex logic is divided into several blocks to achieve a relatively simple, reduce the logic level signal and increase the frequency. The chip area for time, that area of exchange rate.