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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-01-11
  • Size : 5.67mb
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Introduction - If you have any usage issues, please Google them yourself
Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitude (chips generally obtained through look-up table). Generally digitized sine wave output of DDS chip, and therefore need to go through the high-speed D/A converter and a low pass filter to get an analog frequency signal available.
Packet file list
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DDS
...\db
...\..\altsyncram_0f71.tdf
...\..\altsyncram_c841.tdf
...\..\altsyncram_q341.tdf
...\..\DDS.cbx.xml
...\..\DDS.cmp.rdb
...\..\DDS.cmp_merge.kpt
...\..\DDS.db_info
...\..\DDS.hier_info
...\..\DDS.hif
...\..\DDS.lpc.html
...\..\DDS.lpc.rdb
...\..\DDS.lpc.txt
...\..\DDS.map.bpm
...\..\DDS.map.cdb
...\..\DDS.map.hdb
...\..\DDS.map.kpt
...\..\DDS.map.logdb
...\..\DDS.map.qmsg
...\..\DDS.map_bb.cdb
...\..\DDS.map_bb.hdb
...\..\DDS.map_bb.logdb
...\..\DDS.pre_map.cdb
...\..\DDS.pre_map.hdb
...\..\DDS.rpp.qmsg
...\..\DDS.rtlv.hdb
...\..\DDS.rtlv_sg.cdb
...\..\DDS.rtlv_sg_swap.cdb
...\..\DDS.sgate.rvd
...\..\DDS.sgate_sm.rvd
...\..\DDS.sgdiff.cdb
...\..\DDS.sgdiff.hdb
...\..\DDS.sld_design_entry.sci
...\..\DDS.sld_design_entry_dsc.sci
...\..\DDS.smart_action.txt
...\..\DDS.syn_hier_info
...\..\DDS.tis_db_list.ddb
...\..\logic_util_heursitic.dat
...\..\prev_cmp_DDS.map.qmsg
...\..\prev_cmp_DDS.qmsg
...\..\ROM.cbx.xml
...\..\ROM.cmp.rdb
...\..\ROM.cmp_merge.kpt
...\..\ROM.db_info
...\..\ROM.hier_info
...\..\ROM.hif
...\..\ROM.lpc.html
...\..\ROM.lpc.rdb
...\..\ROM.lpc.txt
...\..\ROM.map.bpm
...\..\ROM.map.cdb
...\..\ROM.map.hdb
...\..\ROM.map.kpt
...\..\ROM.map.logdb
...\..\ROM.map.qmsg
...\..\ROM.map_bb.cdb
...\..\ROM.map_bb.hdb
...\..\ROM.map_bb.logdb
...\..\ROM.pre_map.cdb
...\..\ROM.pre_map.hdb
...\..\ROM.rpp.qmsg
...\..\ROM.rtlv.hdb
...\..\ROM.rtlv_sg.cdb
...\..\ROM.rtlv_sg_swap.cdb
...\..\ROM.sgate.rvd
...\..\ROM.sgate_sm.rvd
...\..\ROM.sgdiff.cdb
...\..\ROM.sgdiff.hdb
...\..\ROM.sld_design_entry.sci
...\..\ROM.sld_design_entry_dsc.sci
...\..\ROM.smart_action.txt
...\..\ROM.syn_hier_info
...\..\ROM.tis_db_list.ddb
...\DDS
...\DDS.done
...\DDS.flow.rpt
...\DDS.map.rpt
...\DDS.map.summary
...\DDS.qpf
...\DDS.qpf.bak
...\DDS.qsf
...\DDS.qsf.bak
...\DDS.qws
...\...\db
...\...\..\altsyncram_0f71.tdf
...\...\..\altsyncram_c841.tdf
...\...\..\altsyncram_q341.tdf
...\...\..\DDS.amm.cdb
...\...\..\DDS.asm.qmsg
...\...\..\DDS.asm.rdb
...\...\..\DDS.asm_labs.ddb
...\...\..\DDS.cbx.xml
...\...\..\DDS.cmp.bpm
...\...\..\DDS.cmp.cdb
...\...\..\DDS.cmp.hdb
...\...\..\DDS.cmp.kpt
...\...\..\DDS.cmp.logdb
...\...\..\DDS.cmp.rdb
...\...\..\DDS.cmp2.ddb
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