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digital-clock

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2015-01-12
  • Size : 477kb
  • Downloaded :0次
  • Author :天***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
FPGA write multifunction digital clock, FPGA is ideal for beginner students, as a reference to it.
Packet file list
(Preview for download)


di\clock.asm.rpt
..\clock.done
..\clock.fit.rpt
..\clock.fit.smsg
..\clock.fit.summary
..\clock.flow.rpt
..\clock.map.rpt
..\clock.map.summary
..\clock.pin
..\clock.pof
..\clock.qpf
..\clock.qsf
..\clock.qws
..\clock.sof
..\clock.tan.rpt
..\clock.tan.summary
..\clock.v
..\db\clock.asm.qmsg
..\..\clock.asm_labs.ddb
..\..\clock.cbx.xml
..\..\clock.cmp.cdb
..\..\clock.cmp.hdb
..\..\clock.cmp.kpt
..\..\clock.cmp.logdb
..\..\clock.cmp.rdb
..\..\clock.cmp.tdb
..\..\clock.cmp0.ddb
..\..\clock.cmp2.ddb
..\..\clock.dbp
..\..\clock.db_info
..\..\clock.eco.cdb
..\..\clock.fit.qmsg
..\..\clock.hier_info
..\..\clock.hif
..\..\clock.map.cdb
..\..\clock.map.hdb
..\..\clock.map.logdb
..\..\clock.map.qmsg
..\..\clock.pre_map.cdb
..\..\clock.pre_map.hdb
..\..\clock.psp
..\..\clock.rtlv.hdb
..\..\clock.rtlv_sg.cdb
..\..\clock.rtlv_sg_swap.cdb
..\..\clock.sgdiff.cdb
..\..\clock.sgdiff.hdb
..\..\clock.signalprobe.cdb
..\..\clock.sld_design_entry.sci
..\..\clock.sld_design_entry_dsc.sci
..\..\clock.syn_hier_info
..\..\clock.tan.qmsg
..\db
di
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