Design of FIR filter based on Verilog, the code contains a complete project, can use quartus software to run directly

FIR\db\fir.cbx.xml
...\..\fir.cmp.rdb
...\..\fir.cmp_merge.kpt
...\..\fir.db_info
...\..\fir.hier_info
...\..\fir.hif
...\..\fir.lpc.html
...\..\fir.lpc.rdb
...\..\fir.lpc.txt
...\..\fir.map.bpm
...\..\fir.map.cdb
...\..\fir.map.hdb
...\..\fir.map.kpt
...\..\fir.map.logdb
...\..\fir.map.qmsg
...\..\fir.map_bb.cdb
...\..\fir.map_bb.hdb
...\..\fir.map_bb.logdb
...\..\fir.pre_map.cdb
...\..\fir.pre_map.hdb
...\..\fir.rtlv.hdb
...\..\fir.rtlv_sg.cdb
...\..\fir.rtlv_sg_swap.cdb
...\..\fir.sgdiff.cdb
...\..\fir.sgdiff.hdb
...\..\fir.sld_design_entry.sci
...\..\fir.sld_design_entry_dsc.sci
...\..\fir.smart_action.txt
...\..\fir.syn_hier_info
...\..\fir.tis_db_list.ddb
...\..\fir.tmw_info
...\..\logic_util_heursitic.dat
...\fir.done
...\fir.flow.rpt
...\fir.map.rpt
...\fir.map.summary
...\fir.qpf
...\fir.qsf
...\fir.v
...\incremental_db\compiled_partitions\fir.db_info
...\..............\...................\fir.root_partition.map.cdb
...\..............\...................\fir.root_partition.map.dpi
...\..............\...................\fir.root_partition.map.hdb
...\..............\...................\fir.root_partition.map.kpt
...\..............\README
...\..............\compiled_partitions
...\db
...\incremental_db
FIR

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