quartus ii verilog hdl vga timing project and source code

VGA\db\logic_util_heursitic.dat
...\..\prev_cmp_VGA.qmsg
...\..\VGA.db_info
...\..\VGA.sld_design_entry.sci
...\incremental_db\compiled_partitions\VGA.db_info
...\..............\README
...\VGA.asm.rpt
...\VGA.done
...\VGA.fit.rpt
...\VGA.fit.smsg
...\VGA.fit.summary
...\VGA.flow.rpt
...\VGA.jdi
...\VGA.map.rpt
...\VGA.map.summary
...\VGA.pin
...\VGA.pof
...\VGA.qpf
...\VGA.qsf
...\VGA.qws
...\VGA.sof
...\VGA.sta.rpt
...\VGA.sta.summary
...\VGA.v
...\incremental_db\compiled_partitions
...\db
...\incremental_db
VGA

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