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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-01-23
  • Size : 495kb
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  • Author :j*****
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10-b 50-MHz digital-to-analog (D/A) converter is presented which is based on a dual-ladder resistor string. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 V,,, to 75 Cl
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ieep1.3.pdf
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