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wave_gen_vhd_s6

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-01-23
  • Size : 1.83mb
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  • Author :郑***
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Introduction - If you have any usage issues, please Google them yourself
as the same as its name
Packet file list
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wave_gen_map.xrpt
wave_gen_ngdbuild.xrpt
wave_gen_pad.csv
wave_gen_pad.txt
wave_gen_par.xrpt
wave_gen_pins.ucf
wave_gen_pkg.vhd
wave_gen_summary.html
wave_gen_summary.xml
wave_gen_timing.ucf
wave_gen_usage.xml
wave_gen_vhd_s6.gise
wave_gen_vhd_s6.xise
wave_gen_xst.xrpt
webtalk_pn.xml
_ngo\netlist.lst
.xmsgs\map.xmsgs
......\ngdbuild.xmsgs
......\par.xmsgs
......\pn_parser.xmsgs
......\trce.xmsgs
......\xst.xmsgs
ipcore_dir\blk_mem_gen_readme.txt
..........\char_fifo.asy
..........\char_fifo.gise
..........\char_fifo.ncf
..........\char_fifo.ngc
..........\char_fifo.sym
..........\char_fifo.v
..........\char_fifo.veo
..........\char_fifo.vhd
..........\char_fifo.vho
..........\char_fifo.xco
..........\char_fifo.xise
..........\char_fifo_flist.txt
..........\char_fifo_readme.txt
..........\char_fifo_xmdf.tcl
..........\.lk_core\clk_core.ucf
..........\........\clk_wiz_readme.txt
..........\........\example_design\clk_core_exdes.v
..........\........\..............\clk_core_exdes.vhd
..........\........\implement\implement.bat
..........\........\.........\implement.sh
..........\........\.........\planAhead_ise.bat
..........\........\.........\planAhead_ise.sh
..........\........\.........\planAhead_ise.tcl
..........\........\.........\xst.prj
..........\........\.........\xst.scr
..........\........\simulation\clk_core_tb.v
..........\........\..........\clk_core_tb.vhd
..........\........\..........\functional\simcmds.tcl
..........\........\..........\..........\simulate_isim.bat
..........\........\..........\..........\simulate_isim.sh
..........\........\..........\..........\simulate_mti.do
..........\........\..........\..........\simulate_ncsim.sh
..........\........\..........\..........\simulate_vcs.sh
..........\........\..........\..........\ucli_commands.key
..........\........\..........\..........\vcs_session.tcl
..........\........\..........\..........\wave.do
..........\........\..........\..........\wave.sv
..........\clk_core.asy
..........\clk_core.ejp
..........\clk_core.gise
..........\clk_core.ncf
..........\clk_core.sym
..........\clk_core.v
..........\clk_core.veo
..........\clk_core.vhd
..........\clk_core.vho
..........\clk_core.xco
..........\clk_core.xise
..........\clk_core_exdes.ncf
..........\clk_core_flist.txt
..........\clk_core_xmdf.tcl
..........\coregen.cgc
..........\coregen.cgp
..........\coregen.log
..........\edit_clk_core.tcl
..........\fifo_generator_readme.txt
..........\gen_char_fifo.tcl
..........\samp_ram.asy
..........\samp_ram.gise
..........\samp_ram.ncf
..........\samp_ram.ngc
..........\samp_ram.sym
..........\samp_ram.v
..........\samp_ram.veo
..........\samp_ram.vhd
..........\samp_ram.vho
..........\samp_ram.xco
..........\samp_ram.xise
..........\samp_ram_flist.txt
..........\samp_ram_readme.txt
..........\samp_ram_xmdf.tcl
..........\_xmsgs\cg.xmsgs
..........\......\pn_parser.xmsgs
.seconfig\wave_gen.xreport
.........\wave_gen_vhd_s6.projectmgr
xlnx_auto_0_xdb\cst.xbcd
.st\utilities_lib\utilities_lib.vdbl
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