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DE2_LED_sm

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-01-25
  • Size : 841kb
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  • Author :李***
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DE2 70 development board driver digital tube, and designed a clock counter, clock count, minutes, seconds.
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DE2_LED_sm\7_seg.asm.rpt
..........\7_seg.cdf
..........\7_seg.done
..........\7_seg.dpf
..........\7_seg.eda.rpt
..........\7_seg.fit.rpt
..........\7_seg.fit.smsg
..........\7_seg.fit.summary
..........\7_seg.flow.rpt
..........\7_seg.jdi
..........\7_seg.map.rpt
..........\7_seg.map.summary
..........\7_seg.pin
..........\7_seg.pof
..........\7_seg.qpf
..........\7_seg.qsf
..........\7_seg.qws
..........\7_seg.sof
..........\7_seg.sta.rpt
..........\7_seg.sta.summary
..........\7_seg.tan.rpt
..........\7_seg.tan.summary
..........\7_seg.v
..........\7_seg.v.bak
..........\7_seg_assignment_defaults.qdf
..........\7_seg_description.txt
..........\db\7_seg.amm.cdb
..........\..\7_seg.asm.qmsg
..........\..\7_seg.asm.rdb
..........\..\7_seg.asm_labs.ddb
..........\..\7_seg.atom.rvd
..........\..\7_seg.cbx.xml
..........\..\7_seg.cmp.bpm
..........\..\7_seg.cmp.cdb
..........\..\7_seg.cmp.hdb
..........\..\7_seg.cmp.kpt
..........\..\7_seg.cmp.logdb
..........\..\7_seg.cmp.rdb
..........\..\7_seg.cmp0.ddb
..........\..\7_seg.cmp1.ddb
..........\..\7_seg.cmp_merge.kpt
..........\..\7_seg.db_info
..........\..\7_seg.eda.qmsg
..........\..\7_seg.fit.qmsg
..........\..\7_seg.hier_info
..........\..\7_seg.hif
..........\..\7_seg.idb.cdb
..........\..\7_seg.lpc.html
..........\..\7_seg.lpc.rdb
..........\..\7_seg.lpc.txt
..........\..\7_seg.map.bpm
..........\..\7_seg.map.cdb
..........\..\7_seg.map.hdb
..........\..\7_seg.map.kpt
..........\..\7_seg.map.logdb
..........\..\7_seg.map.qmsg
..........\..\7_seg.map.rdb
..........\..\7_seg.map_bb.cdb
..........\..\7_seg.map_bb.hdb
..........\..\7_seg.map_bb.logdb
..........\..\7_seg.pre_map.cdb
..........\..\7_seg.pre_map.hdb
..........\..\7_seg.root_partition.map.reg_db.cdb
..........\..\7_seg.routing.rdb
..........\..\7_seg.rpp.qmsg
..........\..\7_seg.rtlv.hdb
..........\..\7_seg.rtlv_sg.cdb
..........\..\7_seg.rtlv_sg_swap.cdb
..........\..\7_seg.sgdiff.cdb
..........\..\7_seg.sgdiff.hdb
..........\..\7_seg.sld_design_entry.sci
..........\..\7_seg.sld_design_entry_dsc.sci
..........\..\7_seg.smart_action.txt
..........\..\7_seg.sta.qmsg
..........\..\7_seg.sta.rdb
..........\..\7_seg.sta_cmp.6_slow.tdb
..........\..\7_seg.syn_hier_info
..........\..\7_seg.tis_db_list.ddb
..........\..\7_seg.tmw_info
..........\..\7_seg_global_asgn_op.abo
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_7_seg.asm.qmsg
..........\..\prev_cmp_7_seg.eda.qmsg
..........\..\prev_cmp_7_seg.fit.qmsg
..........\..\prev_cmp_7_seg.map.qmsg
..........\..\prev_cmp_7_seg.qmsg
..........\..\prev_cmp_7_seg.tan.qmsg
..........\incremental_db\compiled_partitions\7_seg.db_info
..........\..............\...................\7_seg.root_partition.cmp.atm
..........\..............\...................\7_seg.root_partition.cmp.cdb
..........\..............\...................\7_seg.root_partition.cmp.dfp
..........\..............\...................\7_seg.root_partition.cmp.hdb
..........\..............\...................\7_seg.root_partition.cmp.hdbx
..........\..............\...................\7_seg.root_partition.cmp.kpt
..........\..............\...................\7_seg.root_partition.cmp.logdb
..........\..............\...................\7_seg.root_partition.cmp.rcf
..........\..............\...................\7_seg.root_partition.cmp.rcfdb
..........\..............\...................\7_seg.root_partition.map.atm
..........\..............\...................\7_seg.root_partition.map.cdb
..........\..............\...................\7_seg.root_partition.map.dpi
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