FPGA-based wireless passthrough module SI4432 VERILOG engineering, testing available

SI4432_TX_192
.............\ADC.v
.............\ADC.v.bak
.............\clk_generator.v
.............\db
.............\..\altsyncram_2i14.tdf
.............\..\altsyncram_4i14.tdf
.............\..\altsyncram_mk14.tdf
.............\..\altsyncram_ok14.tdf
.............\..\altsyncram_pk14.tdf
.............\..\altsyncram_qh14.tdf
.............\..\altsyncram_qk14.tdf
.............\..\altsyncram_rk14.tdf
.............\..\altsyncram_sk14.tdf
.............\..\altsyncram_uso3.tdf
.............\..\cmpr_j4c.tdf
.............\..\cmpr_k4c.tdf
.............\..\cmpr_l4c.tdf
.............\..\cmpr_m4c.tdf
.............\..\cmpr_n4c.tdf
.............\..\cntr_4ti.tdf
.............\..\cntr_64i.tdf
.............\..\cntr_84i.tdf
.............\..\cntr_94i.tdf
.............\..\cntr_a4i.tdf
.............\..\cntr_b4i.tdf
.............\..\cntr_c4i.tdf
.............\..\cntr_cti.tdf
.............\..\cntr_iti.tdf
.............\..\cntr_l2i.tdf
.............\..\cntr_q2i.tdf
.............\..\cntr_r2i.tdf
.............\..\cntr_umi.tdf
.............\..\decode_9jf.tdf
.............\..\logic_util_heursitic.dat
.............\..\mux_lgc.tdf
.............\..\mux_ngc.tdf
.............\..\mux_pgc.tdf
.............\..\prev_cmp_si4432_tx.asm.qmsg
.............\..\prev_cmp_si4432_tx.eda.qmsg
.............\..\prev_cmp_si4432_tx.fit.qmsg
.............\..\prev_cmp_si4432_tx.map.qmsg
.............\..\prev_cmp_si4432_tx.qmsg
.............\..\prev_cmp_si4432_tx.tan.qmsg
.............\..\si4432_tx.amm.cdb
.............\..\si4432_tx.asm.qmsg
.............\..\si4432_tx.asm.rdb
.............\..\si4432_tx.autoh_e4eb1.map.reg_db.cdb
.............\..\si4432_tx.autos_3e921.map.reg_db.cdb
.............\..\si4432_tx.cbx.xml
.............\..\si4432_tx.cmp.bpm
.............\..\si4432_tx.cmp.cdb
.............\..\si4432_tx.cmp.hdb
.............\..\si4432_tx.cmp.kpt
.............\..\si4432_tx.cmp.logdb
.............\..\si4432_tx.cmp.rdb
.............\..\si4432_tx.cmp0.ddb
.............\..\si4432_tx.cmp_merge.kpt
.............\..\si4432_tx.db_info
.............\..\si4432_tx.eda.qmsg
.............\..\si4432_tx.fit.qmsg
.............\..\si4432_tx.hier_info
.............\..\si4432_tx.hif
.............\..\si4432_tx.idb.cdb
.............\..\si4432_tx.lpc.html
.............\..\si4432_tx.lpc.rdb
.............\..\si4432_tx.lpc.txt
.............\..\si4432_tx.map.bpm
.............\..\si4432_tx.map.cdb
.............\..\si4432_tx.map.hdb
.............\..\si4432_tx.map.kpt
.............\..\si4432_tx.map.logdb
.............\..\si4432_tx.map.qmsg
.............\..\si4432_tx.map.rcfdb
.............\..\si4432_tx.map_bb.cdb
.............\..\si4432_tx.map_bb.hdb
.............\..\si4432_tx.map_bb.logdb
.............\..\si4432_tx.merge.qmsg
.............\..\si4432_tx.pre_map.cdb
.............\..\si4432_tx.pre_map.hdb
.............\..\si4432_tx.root_partition.map.reg_db.cdb
.............\..\si4432_tx.rtlv.hdb
.............\..\si4432_tx.rtlv_sg.cdb
.............\..\si4432_tx.rtlv_sg_swap.cdb
.............\..\si4432_tx.sgdiff.cdb
.............\..\si4432_tx.sgdiff.hdb
.............\..\si4432_tx.sld_design_entry.sci
.............\..\si4432_tx.sld_design_entry_dsc.sci
.............\..\si4432_tx.smart_action.txt
.............\..\si4432_tx.smp_dump.txt
.............\..\si4432_tx.sta.qmsg
.............\..\si4432_tx.sta.rdb
.............\..\si4432_tx.sta_cmp.8_slow.tdb
.............\..\si4432_tx.syn_hier_info
.............\..\si4432_tx.tis_db_list.ddb
.............\..\si4432_tx_global_asgn_op.abo
.............\incremental_db
.............\..............\compiled_partitions
.............\..............\...................\si4432_tx.autoh_e4eb1.map.cdb
.............\..............\...................\si4432_tx.autoh_e4eb1.map.dpi

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