EP2C8Q208 TFT LCD color screen VHDL projects, including SDRAM, PLL and other content.

timing_adapter_1_fifo.v
top.v
video_sync_generator.v
.sopc_builder
.............\filters.xml
db
..\myLCD.cmp.rdb
..\myLCD.db_info
..\myLCD.restore.qmsg
incremental_db
..............\compiled_partitions
..............\...................\myLCD.root_partition.map.atm
..............\...................\myLCD.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
ip
..\altera
..\......\sopc_builder_ip
..\......\...............\altera_avalon_pixel_converter
..\......\...............\.............................\altera_avalon_pixel_converter.v
..\......\...............\.............................\altera_avalon_pixel_converter_hw.tcl
..\......\...............\altera_avalon_video_sync_generator
..\......\...............\..................................\altera_avalon_video_sync_generator.v
..\......\...............\..................................\altera_avalon_video_sync_generator_hw.tcl
assignment_defaults.qdf
cpu_0.sdc
cpu_0.v
cpu_0_ic_tag_ram.mif
cpu_0_jtag_debug_module_sysclk.v
cpu_0_jtag_debug_module_tck.v
cpu_0_jtag_debug_module_wrapper.v
cpu_0_oci_test_bench.v
cpu_0_ociram_default_contents.mif
cpu_0_rf_ram_a.mif
cpu_0_rf_ram_b.mif
cpu_0_test_bench.v
jtag_uart_0.v
lcd_pixel_filo.v
lcd_sgdma.v
myLCD.qip
myLCD.qpf
myLCD.qsf
myLCD.restore.rpt
myLCD.sopc
myLCD.v
myLCD_burst_0.v
onchip_memory2_0.hex
onchip_memory2_0.v
out_directory_tmp.txt.tmp
pixel_converter.v
pll1.bsf
pll1.cmp
pll1.ppf
pll1.qip
pll1.vhd
PLLLCD.ppf
PLLLCD.qip
PLLLCD.v
PLLLCD_bb.v
sdram.v
sopc_add_qip_file.tcl
sopc_builder_log.txt
sysid.v
timing_adapter.v
timing_adapter_1.v

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