FPGA to TS201 s link_port interface, 16-bit data format for transmission to the DSP.

dsp_link_tx16\.recordref
.............\AutoConstraint_dsp_link_tx16.sdc
.............\backup\dsp_link_tx16.srr
.............\dsp_link_tx16.edn
.............\dsp_link_tx16.fse
.............\dsp_link_tx16.htm
.............\dsp_link_tx16.ise
.............\dsp_link_tx16.map
.............\dsp_link_tx16.ncf
.............\dsp_link_tx16.prj
.............\dsp_link_tx16.restore
.............\dsp_link_tx16.sap
.............\dsp_link_tx16.sdc
.............\dsp_link_tx16.srd
.............\dsp_link_tx16.srm
.............\dsp_link_tx16.srr
.............\dsp_link_tx16.srs
.............\dsp_link_tx16.szr
.............\dsp_link_tx16.tlg
.............\dsp_link_tx16.vhd
.............\dsp_link_tx16_compile.tcl
.............\dsp_link_tx16_map.tcl
.............\dsp_link_tx16_summary.html
.............\fifo_16x16.asy
.............\fifo_16x16.ngc
.............\fifo_16x16.sym
.............\fifo_16x16.v
.............\fifo_16x16.veo
.............\fifo_16x16.vhd
.............\fifo_16x16.vho
.............\fifo_16x16.xco
.............\rpt_dsp_link_tx16.areasrr
.............\rpt_dsp_link_tx16_areasrr.htm
.............\run_options.txt
.............\stdout.log
.............\synplicity.ucf
.............\...tmp\dsp_link_tx16.plg
.............\......\dsp_link_tx16_flink.htm
.............\......\dsp_link_tx16_srr.htm
.............\......\dsp_link_tx16_toc.htm
.............\......\sap.log
.............\templates\coregen.xml
.............\verif\dsp_link_tx16.vif
.............\.....\dsp_link_tx16_bb.v
.............\dsp_link_tx16_xdb\tmp
.............\backup
.............\coreip
.............\dsp_link_tx16_xdb
.............\syntmp
.............\templates
.............\verif
.............\_xmsgs
dsp_link_tx16

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