Introduction - If you have any usage issues, please Google them yourself
An asynchronous (ripple) counter is a single d-type flip-flop, with its J (data) input fed its own inverted output. This circuit can store one bit, and hence can count zero to one before it overflows (starts over 0). This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition 0 to 1 and a transition 1 to 0. Notice that this creates a new clock with a 50 duty cycle at exactly half the frequency of the input clock. If this output is then used as the clock signal for a similarly arranged D flip-flop (remembering to invert the output to the input), one will get another 1 bit counter that counts half as fast.