sdc parser in tcl by synopsys

sdc2.0.1\eda_result.sdc
........\eda_sample.bat
........\eda_sample.tcl
........\eda_write_sdc.tcl
........\list.txt
........\readme
........\sdc1.1.tcl
........\sdc1.2.tcl
........\sdc1.3.tcl
........\sdc1.4.tcl
........\sdc1.5.tcl
........\sdc1.6.tcl
........\sdc1.7.tcl
........\sdc1.8.tcl
........\sdc1.9.tcl
........\sdc2.0.tcl
........\sdcparser.bat
........\sdcparser.tcl
........\sdcparsercore.tcl
........\sdctest.bat
........\SDC_Parser_UG.pdf
........\tests\all_register1.sdc
........\.....\blue.sdc
........\.....\create_clock_add_latency.sdc
........\.....\create_clock_comment.sdc
........\.....\create_generated_clock_comment.sdc
........\.....\create_voltage_area.sdc
........\.....\cr_gen_clk_20.sdc
........\.....\dc_risc_core.sdc
........\.....\example19.sdc
........\.....\exm17a.sdc
........\.....\exm_sdc19.sdc
........\.....\exm_v1-9-comment.sdc
........\.....\ex_v19.sdc
........\.....\ex_v19.sdccd
........\.....\false_path1.sdc
........\.....\false_path2.sdc
........\.....\gated_clock1.sdc
........\.....\gated_clock2.sdc
........\.....\generated.sdc
........\.....\generated_clock.sdc
........\.....\generated_clockv1.3.sdc
........\.....\generated_dc2000_11.sdc
........\.....\get_cell.sdc
........\.....\get_cells_no_pattern.sdc
........\.....\get_cells_of_object.sdc
........\.....\get_object.sdc
........\.....\get_pins.sdc
........\.....\get_pins15.sdc
........\.....\get_pin_with_wildcard.sdc
........\.....\group_path.sdc
........\.....\group_path2.sdc
........\.....\multicycle1.sdc
........\.....\multicycle2.sdc
........\.....\multicycle3.sdc
........\.....\of_object.sdc
........\.....\pt-testcase1-9.sdc
........\.....\reference_pin.sdc
........\.....\reference_pin2.sdc
........\.....\sample_orca.sdc
........\.....\set_clock_gating_check.sdc
........\.....\set_clock_group.sdc
........\.....\set_clock_latency15.sdc
........\.....\set_clock_unc2.sdc
........\.....\set_clock_uncer1.sdc
........\.....\set_clock_uncertainty.sdc
........\.....\set_clock_uncertainty15.sdc
........\.....\set_data_check.sdc
........\.....\set_delay.sdc
........\.....\set_disable_timing.sdc
........\.....\set_driving_cell.sdc
........\.....\set_driving_cell1.sdc
........\.....\set_input_trasition.sdc
........\.....\set_i_trans.sdc
........\.....\set_level_shifter_strategy.sdc
........\.....\set_level_shifter_threshold.sdc
........\.....\set_max_delay.sdc
........\.....\set_max_leakage.sdc
........\.....\set_min_porosity.sdc
........\.....\set_min_pulse_width.sdc
........\.....\set_output_delay_with_latency.sdc
........\.....\set_timing_derate.sdc
........\.....\set_unit1.sdc
........\.....\set_vol.sdc
........\.....\set_voltage.sdc
........\.....\set_voltage1.sdc
........\.....\set_wire_load_selection_group.sdc
........\.....\s_c_un.sdc
........\.....\t2.sdc
........\.....\temp.sdc
........\.....\test1.sdc
........\.....\test2.sdc
........\.....\test3.sdc
........\.....\test5.sdc
........\.....\test_1.4.sdc
........\.....\test_for_sdc_1.2.sdc
........\.....\timing1.sdc
........\...._scripts\0_usage
........\............\0_usage.bat
........\............\1_simple

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