puls wide modulator based on delayline

delayline_b\clock.bsf
...........\clock.v
...........\clock.v.bak
...........\db\delayline_b.db_info
...........\..\delayline_b.eco.cdb
...........\..\delayline_b.sld_design_entry.sci
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_delayline_b.qmsg
...........\delayline_b.asm.rpt
...........\delayline_b.bdf
...........\delayline_b.done
...........\delayline_b.eda.rpt
...........\delayline_b.fit.rpt
...........\delayline_b.fit.smsg
...........\delayline_b.fit.summary
...........\delayline_b.flow.rpt
...........\delayline_b.map.rpt
...........\delayline_b.map.smsg
...........\delayline_b.map.summary
...........\delayline_b.pin
...........\delayline_b.qpf
...........\delayline_b.qsf
...........\delayline_b.qws
...........\delayline_b.sof
...........\delayline_b.sta.rpt
...........\delayline_b.sta.summary
...........\delayline_b_nativelink_simulation.rpt
...........\incremental_db\compiled_partitions\delayline_b.db_info
...........\..............\...................\delayline_b.root_partition.cmp.cdb
...........\..............\...................\delayline_b.root_partition.cmp.dfp
...........\..............\...................\delayline_b.root_partition.cmp.hdb
...........\..............\...................\delayline_b.root_partition.cmp.kpt
...........\..............\...................\delayline_b.root_partition.cmp.logdb
...........\..............\...................\delayline_b.root_partition.cmp.rcfdb
...........\..............\...................\delayline_b.root_partition.map.cdb
...........\..............\...................\delayline_b.root_partition.map.dpi
...........\..............\...................\delayline_b.root_partition.map.hbdb.cdb
...........\..............\...................\delayline_b.root_partition.map.hbdb.hb_info
...........\..............\...................\delayline_b.root_partition.map.hbdb.hdb
...........\..............\...................\delayline_b.root_partition.map.hbdb.sig
...........\..............\...................\delayline_b.root_partition.map.hdb
...........\..............\...................\delayline_b.root_partition.map.kpt
...........\..............\README
...........\simulation\modelsim\delayline_b.sft
...........\..........\........\delayline_b.vo
...........\..........\........\delayline_b_6_1200mv_0c_slow.vo
...........\..........\........\delayline_b_6_1200mv_0c_v_slow.sdo
...........\..........\........\delayline_b_6_1200mv_85c_slow.vo
...........\..........\........\delayline_b_6_1200mv_85c_v_slow.sdo
...........\..........\........\delayline_b_min_1200mv_0c_fast.vo
...........\..........\........\delayline_b_min_1200mv_0c_v_fast.sdo
...........\..........\........\delayline_b_modelsim.xrf
...........\..........\........\delayline_b_run_msim_rtl_verilog.do
...........\..........\........\delayline_b_run_msim_rtl_verilog.do.bak
...........\..........\........\delayline_b_run_msim_rtl_verilog.do.bak1
...........\..........\........\delayline_b_v.sdo
...........\..........\........\modelsim.ini
...........\..........\........\msim_transcript
...........\..........\........\rtl_work\clock\verilog.prw
...........\..........\........\........\.....\verilog.psm
...........\..........\........\........\.....\_primary.dat
...........\..........\........\........\.....\_primary.dbs
...........\..........\........\........\.....\_primary.vhd
...........\..........\........\........\_info
...........\..........\........\........\_vmake
...........\..........\........\........\clock
...........\..........\........\........\_temp
...........\..........\........\rtl_work
...........\incremental_db\compiled_partitions
...........\simulation\modelsim
...........\db
...........\incremental_db
...........\simulation
delayline_b

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