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PHY_MDIO

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-03-17
  • Size : 1.06mb
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Introduction - If you have any usage issues, please Google them yourself
Fiber-point communication module, Gigabit Ethernet transmission, based on FPGA, using Verilog language programming, high-speed transmission of Gigabit Ethernet Module
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PHY_MDIO
........\.sopc_builder
........\.............\filters.xml
........\.............\install.ptf
........\.............\install2.ptf
........\.............\preferences.xml
........\clkdiv.v
........\clkdiv.v.bak
........\db
........\..\altsyncram_2q14.tdf
........\..\altsyncram_elg1.tdf
........\..\altsyncram_up14.tdf
........\..\cmpr_5cc.tdf
........\..\cmpr_8cc.tdf
........\..\cmpr_acc.tdf
........\..\cntr_02j.tdf
........\..\cntr_0ci.tdf
........\..\cntr_2ci.tdf
........\..\cntr_gui.tdf
........\..\cntr_sbi.tdf
........\..\decode_rqf.tdf
........\..\logic_util_heursitic.dat
........\..\mux_aoc.tdf
........\..\phy_mdio_controller.db_info
........\..\phy_mdio_controller.eco.cdb
........\..\phy_mdio_controller.sld_design_entry.sci
........\..\prev_cmp_phy_mdio_controller.qmsg
........\..\sopcb_tb2_unnamed.xml
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\phy_mdio_controller.autoh_e4eb1.map.cdb
........\..............\...................\phy_mdio_controller.autoh_e4eb1.map.dpi
........\..............\...................\phy_mdio_controller.autoh_e4eb1.map.hdb
........\..............\...................\phy_mdio_controller.autoh_e4eb1.map.kpt
........\..............\...................\phy_mdio_controller.autoh_e4eb1.map.logdb
........\..............\...................\phy_mdio_controller.autos_3e921.map.cdb
........\..............\...................\phy_mdio_controller.autos_3e921.map.dpi
........\..............\...................\phy_mdio_controller.autos_3e921.map.hdb
........\..............\...................\phy_mdio_controller.autos_3e921.map.kpt
........\..............\...................\phy_mdio_controller.autos_3e921.map.logdb
........\..............\...................\phy_mdio_controller.db_info
........\..............\...................\phy_mdio_controller.root_partition.cmp.cdb
........\..............\...................\phy_mdio_controller.root_partition.cmp.dfp
........\..............\...................\phy_mdio_controller.root_partition.cmp.hdb
........\..............\...................\phy_mdio_controller.root_partition.cmp.kpt
........\..............\...................\phy_mdio_controller.root_partition.cmp.logdb
........\..............\...................\phy_mdio_controller.root_partition.cmp.rcfdb
........\..............\...................\phy_mdio_controller.root_partition.map.cdb
........\..............\...................\phy_mdio_controller.root_partition.map.dpi
........\..............\...................\phy_mdio_controller.root_partition.map.hbdb.cdb
........\..............\...................\phy_mdio_controller.root_partition.map.hbdb.hb_info
........\..............\...................\phy_mdio_controller.root_partition.map.hbdb.hdb
........\..............\...................\phy_mdio_controller.root_partition.map.hbdb.sig
........\..............\...................\phy_mdio_controller.root_partition.map.hdb
........\..............\...................\phy_mdio_controller.root_partition.map.kpt
........\..............\README
........\master_0
........\master_0.v
........\........\altera_avalon_packets_to_master
........\........\...............................\altera_avalon_packets_to_master.v
........\........\altera_avalon_sc_fifo
........\........\.....................\altera_avalon_sc_fifo.v
........\........\altera_avalon_st_bytes_to_packets
........\........\.................................\altera_avalon_st_bytes_to_packets.v
........\........\altera_avalon_st_packets_to_bytes
........\........\.................................\altera_avalon_st_packets_to_bytes.v
........\........\altera_jtag_avalon_master
........\........\.........................\master_0_master_0.v
........\........\altera_jtag_dc_streaming
........\........\........................\altera_avalon_st_clock_crosser.v
........\........\........................\altera_avalon_st_idle_inserter.v
........\........\........................\altera_avalon_st_idle_remover.v
........\........\........................\altera_avalon_st_jtag_interf
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